Optimized Silicon-Rich Oxide (SRO) Deposition Process for 5-V-Only Flash EEPROM Applications

IEEE Electron Device Letters

Volumn 14, Issue 6, 1993, Pages 283-285

  Dori, Leonello ^a   Acovic, Alexandre ^b   DiMaria, Donelli J ^b   Hsu, Ching Hsiang ^b  

^a CNR   (Italy)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; DIELECTRIC MATERIALS; MOS DEVICES; OXIDES; PROM;

EEPROM APPLICATIONS; LPCVD REACTOR; OPTIMIZED SILICON-RICH OXIDE (SRO) DEPOSITION PROCESS; POLYSILICON-GATE MOS CAPACITORS; STACKED DIELECTRIC STRUCTURES;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 0027606480     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.215199     Document Type: Article

References (4)

1. 2films and experimental applications,” J. Appl. Phys., vol. 51, p. 2722, 1980.
2. D. J. DiMaria, K. M. Demeyer, and D. W. Dong, “Electrically-alterable memory using a dual electron injector structure,” IEEE Electron Device Lett., vol. 1, p. 179, 1980.
3. D. J. DiMaria, D. W. Dong, and F. L. Pesavento, “Enhanced conduction and minimized charge trapping in electrically alterable read-only memories using off-stochiometric silicon dioxide films,” J. Appl. Phys., vol. 55, p. 3000, 1984.
4. J. Maserjian and N. Zamani, “Behavior of the Si/SiO 2 interface observed by Fowler-Nordheim tunneling,” J. Appl. Phys., vol. 54, p. 559, 1982.