Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 2, 2000, Pages 207-216

  Vermeulen, Frederik ^a,b   Catthoor, Francky ^a,b   Verkest, Diederik ^a,c   De Man, Hugo ^a,b  

^a IEEE

^b UNIVERSITY OF LEUVEN   (Belgium)

^c IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SYSTEMS PROGRAMMING; DATA STORAGE EQUIPMENT; DATA TRANSFER; MATHEMATICAL MODELS; MULTIMEDIA SYSTEMS; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS); ULSI CIRCUITS;

EMBEDDED DATA-DOMINATED APPLICATIONS;

EMBEDDED SYSTEMS;

EID: 0033879207     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.831440     Document Type: Article

References (28)

1. R. W. Brodersen, "The network computer and its future, "in IEEE Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 1997, pp. 32-36.
2. A. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W. Brodersen, "Optimizing power using transformations," IEEE Trans. Computer-Aided Design, vol. 14, pp. 1-30, Jan. 1995.
3. T. Meng, B. Gordon, E. Tsern, and A. Hung, "Portable video-on-demand in wireless communication," Proc. IEEE, vol. 83, pp. 659-680, Apr. 1995.
4. V. Tiwari, S. Malik, A. Wolfe, and M. Lee, "Instruction-level power analysis and optimization of software," J. VLSI Signal Processing, no. 13, pp. 223-238, 1996.
5. F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. De Man, "Global communication and memory optimizing transformations for low power signal processing systems," in IEEE Workshop on VLSI Signal Processing, La Jolla, CA, Oct. 1994.
6. R. Gupta and Y. Zorian, "Introducing core-based system design," IEEE Design and Test of Computers, vol. 14, pp. 15-25, Oct. 1997.
7. VSI Alliance Architecture Document, 1.0 ed., VSI Alliance, 1997.
8. J. Öberg, A. Kumar, and A. Jantsch, "An object-oriented concept for intelligent library functions," in Proc. VLSI Design '98 Conf., Chenai, India, Jan. 1998, pp. 355-358.
9. M. Koegst, P. Conradi, D. Garte, and M. Wahl, "A systematic analysis of reuse strategies for design of electronic circuits," in Proc. DATE '98 Conf., Pans, France, Feb. 1998, pp. 292-296.
10. A. Jerraya, H. Ding, P. Kission, and M. Rahmouni, Behavioral Synthesis and Component Reuse with VHDL. Norwell, MA: Kluwer, 1997.
11. O. Bringmann and W. Rosenstiel, "Resource sharing in hierarchical synthesis," in Int. Conf. CAD, San Jose, CA, Nov. 1997, pp. 318-325.
12. D. Rao and F. Kurdahi, "Hierarchical design space exploration for a class of digital systems," IEEE Trans. VLSI Syst., vol. 1, pp. 282-295, Sept. 1993.
13. D. Singh, J. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T. Mozdzen, "Power conscious CAD tools and methodologies: A perspective," Proc. IEEE, vol. 83, pp. 570-594, Apr. 1995.
14. A. Chandrakasan and R. Brodersen, Eds., Low Power CMOS Design. New York: IEEE Press, 1998.
15. F. Catthoor, S. Wuytack, E. De Greef, F. Franssen, L. Nachtergaele, and H. De Man, "System-level transformations for low power data transfer and storage," in Paper Collection on Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Eds. New York: IEEE Press, 1998, pp. 609-618.
16. P. Panda, N. Dutt, and A. Nicolau, "Local memory exploration and optimization in embedded systems," IEEE Trans. Computer-Aided Design, vol. 18, pp. 3-13, Jan. 1999.
17. L. Nachtergaele, F. Catthoor, B. Kapoor, D. Moolenaar, and S. Janssens, "Low power storage exploration for H.263 video decoder," in IEEE Workshop on VLSI Signal Processing, Monterey, CA, Oct. 1996.
18. F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle, Custom Memory Management Methodology - Exploration of Memory Organization for Embedded Multimedia System Design. Norwell, MA: Kluwer, 1998.
19. D. Moolenaar, L. Nachtergaele, F. Catthoor, and H. De Man, "System-level power exploration for MPEG-2 decoder on embedded cores: A systematic approach," in Proc. IEEE Workshop on Signal Processing Systems, Leicester, U.K., Nov. 1997, pp. 395-404.
20. E. Lee and A. Sangiovanni-Vincentelli, "A framework for comparing models of computation," IEEE Trans. Computer-Aided Design, vol. 17, pp. 1217-1229, Dec. 1998.
21. D. Lanneer, "Design models and data-path mapping for signal processing architectures," Ph.D. dissertation, Katholieke Universiteit Leuven, Belgium, Mar. 1993.
22. F. Franssen, F. Balasa, M. van Swaaij, F. Catthoor, and H. De Man, "Modeling multidimensional data and control flow," IEEE Trans. VLSI Syst., vol. 1, Sept. 1993.
23. E. De Greef, "Storage size reduction for multimedia applications," Ph.D. dissertation, Katholieke Universiteit Leuven, Belgium, Jan. 1998.
24. F. Thoen, J. Van Der Steen, G. De Jong, G. Goossens, and H. De Man, "Multi-thread graph - A system model for real-time embedded software synthesis," in Proc. European Design and Test Conf., Paris, France, Mar. 1997, pp. 476-481.
25. Asymmetric Digital Subscriber Loop Standard, ANSI T1E1.4 Committee, Contribution 95-007, June 1995.
26. Telenor's H.263 Software, "Digital video coding at Telenor R&D" [On-line]. Available: http://www.nta.no/brukere/DVC/h263_software/.
27. K. Danckaert, K. Masselos, F. Catthoor, H. De Man, and C. Goutis, "Strategy for power efficient design of parallel systems," IEEE Trans. VLSI Syst., vol. 7, June 1999.
28. F. Vermeulen, F. Catthoor, D. Verkest, and H. De Man, "A system-level reuse methodology for embedded data-dominatedapplications," in IEEE Workshop on Signal Processing Systems, Boston, MA, Oct. 1998, pp. 551-560.