A systematic analysis of reuse strategies for design of electronic circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 292-296

  Koegst, Manfred ^a   Conradi, Peter ^b   Garte, Dieter ^a   Wahl, Michael ^b  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS IIS   (Germany)

^b UNIVERSITY OF SIEGEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNS; CORE MODEL; DESIGN ISSUES; REUSE STRATEGY; SYSTEMATIC ANALYSIS;

DESIGN;

EID: 0004594781     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655871     Document Type: Conference Paper

References (19)

1. Aamont, A.; Plaza, E.: Case-Based Reasoning: Foundational Issues, Methodological Variations, and System Approaches. AICOM Vol. 7, No. 1, March 1994.
2. Altmeyer, J.; Ohnsorge, St.; Schürmann, B.: Reuse of Design Objects in CAD Frameworks. Proceedings of the International Conference on Computer Aided Design, San Jose, California, 1994.
3. Bergmann, R.,: Effizientes Problemlösen durch flexible Wiederverwendung von Fällen auf verschiedenen Abstraktionsebenen. Dissertation Universität Kaiserslautern, 1996.
4. Bergmann, R., Munioz, H., Veloso, M.: Fallbasiertes Planen: Ausgewählte Methoden und Systeme, Künstliche Intelligenz, 1/1996.
5. Conradi, P.: Reuse-dominated Synthesis of electronic designs, 4th biennial Baltic Electronics Conference, Tallinn, Estonia, October 9-14, 1994.
6. Conradi, P.: Information Model of a Compound Graph Presentation for System and Architecture Level Design. EURO-DAC 95, pp. 22-27.
7. Frakes, W.B.; Fox, C.J.: Sixteen questions about software reuse. Communications of the ACM, 38(6), pp. 75-87, June 1995.
8. Girczyc, E.; Carlson, St.: Increasing Design Quality and Engineering Productivity through Design Reuse. DAC 93, pp. 48-53.
9. Jerraya, A.A.; Ding, H.; Kission, P.; Rahmouni, M.: Behavioral Synthesis and Component Reuse with VHDL. Kluwer Academic Publishers, Boston/ London/ Dortrecht, 1997.
10. Jha, P.; Dutt, N.D.: Design Reuse Through High-Level Library Mapping. European Design and Test Conference, Paris, 1995, pp. 345-350.
11. Kission, P.; Ding, H.; Jerraya, A.A.: VHDL Based Design Methodology for Hierarchy and Component Re-Use. EURO-DAC 95, pp. 470-475.
12. Koegst, M.; Conradi, P.; Garte, D.; Wahl, M.: Analysis and Classification of Reuse Strategies and Tasks for the Circuit Design, IWLAS97, Grenoble.
13. Lehmann, G.; Wunder, B.; Müller-Glaser, K.D.: A VHDL Reuse Workbench. EURO-DAC 96, pp. 412-417.
14. Nebel, W.; Schumacher, G.: Object-Oriented Hardware Modelling-Where to apply and what are the objects? EURO-DAC 96, pp. 428-433.
15. Preis, V.; Henftling, R.; Schütz, M.; März-Rössel, S.: A Reuse-Based Hardware Design Flow. EURODAC 95, pp. 464-469.
16. Reutter, A.; Mößner, B.; Kreutzer, I; Rosenstiel, W.: Wiederverwendung komplexer Komponenten für Synthese und Simulation unter Verwendung von VHDL. 8. E.I.S.-Workshop,8.-9. Apr.1997, Hamburg, 105-114.
17. Ross, D.T.: Applications and Extensions of SADT, Computer, April 1985.
18. Seepold, R.; Kunzmann, A.; Rosenstiel, W.: Eine effiziente objekt-orientierte Wiederverwendungsmethode für den Hardware-Design. 8. E.I.S.-Workshop, 8.-9. April 1997, Hamburg, 125-131.
19. Synopsys Design Ware Developer Guide", Synopsys Inc., Montain View, CA,97 1997.