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Volumn 46, Issue 6, 1997, Pages 709-716

Easily testable realizations for generalized Reed-Muller expressions

Author keywords

AND EXOR; Circuit complexity; Linear circuit; Logic minimization; Reed Muller expression; Testable design

Indexed keywords


EID: 0000049072     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.600830     Document Type: Article
Times cited : (59)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.