Testability of 2-level AND/EXOR circuits

Proceedings of European Design and Test Conference

Volumn , Issue , 1997, Pages 548-553

  Drechsler, Rolf ^a   Hengster, Harry ^a   Schaefer, Horst ^a   Hartmann, Joachim ^a   Becker, Bernd ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; ELECTRIC NETWORK ANALYSIS; LOGIC GATES; PROBABILISTIC LOGICS; RANDOM PROCESSES;

FIXED POLARITY REED MULLER EXPRESSIONS; INPUT PROBABILITY DISTRIBUTION; POSITIVE POLARITY REED MULLER EXPRESSIONS;

LOGIC CIRCUITS;

EID: 0030652725     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)