CMOS edge-triggered flip-flop using one latch

Electronics Letters

Volumn 34, Issue 16, 1998, Pages 1581-1582

  Wu, X ^a   Wei, J ^a  

^a ZHEJIANG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN;

EDGE-TRIGGERED FLIP-FLOPS;

FLIP FLOP CIRCUITS;

EID: 0032490822     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19981095     Document Type: Article

References (3)

1. WEST, N.H., and ESHRAGHIAN, E.K.: 'Principles of CMOS VLSI design: A system perspective' (Addison-Wesley Publishing Co., New York 1993), 2nd Edn., Chap. 5
2. PEDRAM, M.: 'Power minimization in IC design: Principles and applications', ACM Trans. Design Autom. Electron. Syst., 1996, 1, (1), pp. 3-56
3. WU, X., and DENG, X.: 'Edge-triggered flip-flop based on clock signal racing', J. Hangzhou University, 1990, 17, (4), pp. 417-422