7.4 to 8.4 GHz high efficiency PHEMT three-stage power amplifier

IEEE MTT-S International Microwave Symposium Digest

Volumn 2, Issue , 2000, Pages 947-950

  Chu, S L G ^a   Platzker, A ^a   Borkowski, M ^a   Mallavarpu, R ^a   Snow, M ^a   Bowlby, A ^a   Teeter, D ^a   Kazior, T ^a   Alavi, K ^a  

^a Advanced Device Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTINUOUS WAVE POWER OUTPUT; LOAD PULL MEASUREMENT; MATERKA MODEL; POWER ADDED EFFICIENCY;

CAPACITANCE; CAPACITORS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; GAIN MEASUREMENT; GATES (TRANSISTOR); HIGH ELECTRON MOBILITY TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MONOLITHIC MICROWAVE INTEGRATED CIRCUITS; RESISTORS; SEMICONDUCTING GALLIUM ARSENIDE;

POWER AMPLIFIERS;

EID: 0033678425     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (9)

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9. R. Mallavarpu, D. Teeter, M. Snow, "The Importance of Gate Charge Formulation in Large-Signal PHEMT Modeling," IEEE GaAs IC Symposium Digest, pp 87-90, 1998.