Testability of convergent tree circuits

IEEE Transactions on Computers

Volumn 45, Issue 8, 1996, Pages 950-963

  Blanton, R D ^a,b   Hayes, John P ^a,c  

^a IEEE

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

C testability; Design for testability; Functional testing; Iterative logic arrays; Regular circuits; Synthesis for testability; Test generation; Testability; Tree circuits

Indexed keywords

COMPUTER SYSTEM RECOVERY; ELECTRIC NETWORK SYNTHESIS; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC CIRCUITS; TREES (MATHEMATICS);

CIRCUIT TESTABILITY; CONVERGENT TREE CIRCUITS; FUNCTIONAL TESTING; REGULAR CIRCUITS; TEST GENERATION;

COMPUTER CIRCUITS;

EID: 0030215984     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.536237     Document Type: Article

References (18)

1. J. Abraham and D. Gajski, "Design of Testable Structures Defined by Simple Loops," IEEE Trans. Computers, vol. 30, pp. 875-883, 1981.
2. M. Abramovici, "Dos and Don'ts in Computing Fault Coverage," Proc. 1993 Int'l Test Conf., p. 594, 1993.
3. M. Abramovici, M.A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. Potomac, Md.: Computer Science Press, 1990.
4. B. Becker, "Efficient Testing of Optimal Time Adders," IEEE Trans. Computers, vol. 37, pp. 1,113-1,120, 1988.
5. D. Bhattacharya and J.F. Hayes, "Designing for High-Level Test Generation," IEEE Trans. Computer-Aided Design, vol. 9, pp. 752-766, 1990.
6. R.S. Blanton and J.P. Hayes, "Efficient Testing of Tree Circuits," Proc. 23rd Int'l Symp. Fault-Tolerant Computing, pp. 176-185, June 1993.
7. W.T. Cheng, "Testing and Error Detection in Iterative Logic Arrays," PhD thesis, Technical Report no. UILU-ENG-85-2234 CSG-44, Univ. of Illinois at Urbana-Champaign, 1985.
8. A.D. Friedman, "Easily Testable Iterative Systems," IEEE Trans. Computers, vol. 22, pp. 1,061-1,064, 1973.
9. W.H. Kautz, "Testing for Faults in Cellular Logic Arrays," Proc. Eighth Symp. Switching and Automation Theory, pp. 161-174, 1967.
10. K.L. Kodandapani and S.C. Seth, "On Combinational Networks with Restricted Fanout," IEEE Trans. Computers, vol. 27, pp. 309-318, 1978.
11. F. Lombardi and D. Sciuto, "Constant Testability of Combinational Cellular Tree Structures," J. Electronic Testing: Theory and Applications, vol.3, pp. 139-148, May 1992.
12. T. Lynch and E.E. Swartzlander, "A Spanning Tree Carry Lookahead Adder," IEEE Trans. Computers, vol. 41, pp. 931-939, 1992.
13. P.C. Maxwell, "Let's Grade All the Faults," Proc. 1993 Int'l Test Conf., p. 595, Oct. 1993.
14. R. Parthasarathy and S. Reddy, "A Testable Design of Iterative Logic Arrays," IEEE Trans. Circuits and Systems, vol. 28, pp. 1,037-1,045, 1981.
15. J.M. Soden and C.F. Hawkins, "Quality Testing Requires Quality Thinking," Proc. 1993 Int'l Test Conf., p. 596, Oct. 1993.
16. T. Sridhar and J.P. Hayes, "Design of Easily Testable Bit-Sliced Systems," IEEE Trans. Computers, vol. 30, pp. 842-854, 1981.
17. C. Wu and P. Cappello, "Easily Testable Iterative Logic Arrays," IEEE Trans. Computers, vol. 39, pp. 640-652, 1990.
18. Y. You and J.P. Hayes, "Implementation of VLSI Self-Testing by Regularization," IEEE Trans. Computer-Aided Design, vol. 8, pp. 1,261-1,271, 1989.