4.1 ns compact 54×54 b multiplier utilizing sign select booth encoders

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 416-417

  Inoue, Atsuki ^a   Ohe, Ryoichi ^a   Kashiwakura, Shoichiro ^a   Mitarai, Shin ^a   Tsuru, Takayuki ^a   Izawa, Tetsuo ^a   Goto, Gensuke ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER WORKSTATIONS; COST EFFECTIVENESS; DIGITAL ARITHMETIC; IMAGE QUALITY; MICROPROCESSOR CHIPS; PERSONAL COMPUTERS; THREE DIMENSIONAL COMPUTER GRAPHICS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS; VLSI CIRCUITS;

BOOTH SELECTORS; ELECTRON BEAM PROBING; SIGN SELECT BOOTH ENCODERS;

MULTIPLYING CIRCUITS;

EID: 0031073614     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)