1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 1996, Pages 1037-1040

  Cheng, Kuo Hsing ^a   Yee, Liow Yu ^a  

^a TAMKANG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC CURRENT CONTROL; ENERGY EFFICIENCY; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS;

LOW POWER CURRENT SENSING COMPLEMENTARY PASS TRANSISTOR LOGIC; SOFTWARE PACKAGE HSPICE;

MULTIPLYING CIRCUITS;

EID: 0030349946     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)