Performing Arithmetic Functions with the Chinese Abacus Approach

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 46, Issue 12, 1999, Pages 1512-1515

  Maloberti, F ^a   Gang, C ^b  

^a UNIVERSITY OF PAVIA   (Italy)

^b HUNAN NORMAL UNIVERSITY   (China)

Author keywords

Chinese abacus; Digital arithmetic; Multiplier

Indexed keywords

ADDERS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; FORMAL LOGIC; MULTIPLYING CIRCUITS; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); TRANSISTORS;

CHINESE ABACUS; DOMINO LOGIC; PASS TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 0033281127     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.809537     Document Type: Article

References (4)

1. R. Zimmerman and W. FichtnerLow-power logic styles: CMOS versus pass transistor logic, IEEE J. Solid-State Circuits, vol. 32, pp. 1079-1090, July 1997.
2. M. Hanawa, K. Kaneko, et. al, A 4.3 ns 0.3 mm CMOS 54x 54 multiplier using préchargea pass-transistor logic, in Proc. ISSCC'96, pp. 364-365.
3. S. NaffzigerA sub-nanosecond 0.5 mm 64 b adder design, in Proc. ISSCC'96, pp. 362-363.
4. A. Inoue, R. Ohé, et alA 4.1 ns compact 54x54 multiplier utilizing sing select booth encoders, in Proc. ISSCC'97, pp. 416-417.