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0029253945
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A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM
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K. Imamiya, Y. Iwata, Y. Sugiura, H. Nakamura, H. Oodaira, M. Momodomi, Y. Ito, T. Watanabe, H. Araki, K. Narita, K. Masuda, and J. Miyamoto, "A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 130-131.
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A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
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K. Suh, B. Shu, Y. Lim, J. Kim, Y. Choi, Y. Koh, S. Lee, S. Kwon, B. Choi, J. Lum, J. Choi, J. Kim, and H. Lim, "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 128-129.
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Suh, K.1
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A 34 Mb 3.3 V serial flash EEPROM for solid-state disk applications
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R. Cernea, D. Lee, M. Mofidi, E. Chang, W. Chien, L. Goh, Y. Fong, J. Yuan, G. Samachisa, D. Guterman, S. Mehrotra, K. Sato, H. Onishi, K. Ueda, F. Noro, K. Miyamoto, M. Morita, K. Umeda, and K. Kubo, "A 34 Mb 3.3 V serial flash EEPROM for solid-state disk applications," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 126-127.
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0029714787
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2 64 Mb NAND flash memory achieving 180 ns/Byte effective program speed
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2 64 Mb NAND flash memory achieving 180 ns/Byte effective program speed," in Symp. VLSI Circuits Dig. Tech. Papers, June 1996, pp. 168-169.
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0028752012
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2 self-aligned shallow trench isolation cell (SA-STI CELL) for 3 V-only 256 Mbit NAND EEPROM's
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2 NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memories
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2 NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memories," in IEDM Tech. Dig., Dec. 1997, pp. 271-274.
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0031634344
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A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories
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Y. Takeuchi, K. Shimizu, K. Narita, E. Kamiya, T. Yaegashi, K. Ameniya, and S. Aritome, "A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories," in Symp. VLSI Technology Dig. Tech. Papers, June 1998, pp. 102-103.
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Bitline clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories
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T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, and K. Kimura, "Bitline clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories," IEEE J. Solid-State Circuits, vol. 31, pp. 1590-1600, Nov. 1996.
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0028538112
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A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory
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T. Tanaka, Y. Tanaka, H. Nakamura, K. Sakui, H. Oodaira, R. Shirota, K. Ohuchi, F. Masuoka, and H. Hara, "A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory," IEEE J. Solid-State Circuits, vol. 29, pp. 1366-1373, Nov. 1994.
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