1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1997, Pages 103-104

  Lee, K C ^a   Yoon, H ^a   Lee, S B ^a   Lee, J H ^a   Moon, B S ^a   Kim, K Y ^a   Kim, C H ^a   Cho, S I ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; TRANSISTORS;

HIERARCHICAL DECODING SCHEME;

RANDOM ACCESS STORAGE;

EID: 0031374804     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)