Automated Hierarchical CMOS Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 3, 1999, Pages 304-317

  Naiknaware, Ravindranath ^a,b,c   Fiez, Terri S ^a,d,e,f,g,h  

^a WASHINGTON STATE UNIVERSITY   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^c TEXAS INSTRUMENTS   (India)

^d UNIVERSITY OF IDAHO   (United States)

^e OREGON STATE UNIVERSITY   (United States)

^f HEWLETT PACKARD COMPANY   (United States)

^g Washington State University   (United States)

^h AKM Design Tek   (United States)

Author keywords

CMOS analog integrated circuits; Design automation; Design methodology; Integrated circuit layout

Indexed keywords

AUTOMATION; INTEGRATED CIRCUIT LAYOUT; TRANSISTORS;

ANALOG CIRCUIT STACK GENERATION;

CMOS INTEGRATED CIRCUITS;

EID: 0033100433     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.748182     Document Type: Article

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