Simulation-based techniques for dynamic test sequence compaction

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 67-73

  Rudnick, Elizabeth M ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FAILURE ANALYSIS; GENETIC ALGORITHMS; INTEGRATED CIRCUIT TESTING;

BENCHMARK CIRCUITS; DETERMINISTIC TEST GENERATOR; FAULT SIMULATOR;

SEQUENTIAL CIRCUITS;

EID: 0030400116     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)