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Volumn 42, Issue 3, 1999, Pages 66-81

Spiral inductor substrate loss modeling in silicon RFICs

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY OF SOLIDS; ELECTRIC LOSSES; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; RESONANT CIRCUITS; SEMICONDUCTOR DEVICE MODELS; SILICON WAFERS;

EID: 0033098283     PISSN: 01926225     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article
Times cited : (23)

References (19)
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  • 2
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  • 4
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  • 5
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    • P.C. Yue and S.S. Wong, "On-chip Spiral Inductors with Patterned Ground Shields for Si-based RFICs," IEEE Symposium on VLSI Circuits, 1997, pp. 85-86.
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  • 9
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  • 10
    • 0010283229 scopus 로고
    • Designing inductors for thin-film applications
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  • 11
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    • Center-tapped spiral inductors for monolithic bandpass filters
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  • 12
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  • 13
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  • 14
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  • 16
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  • 17
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.