Interface timing verification with delay correlation using constraint logic programming

Proceedings of the 1997 European Conference on Design and Test, EDTC 1997

Volumn , Issue , 1997, Pages 12-19

  Girodias, Pierre ^a   Cerny, Eduard ^a  

^a UNIVERSITÉ DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; CONSTRAINT SATISFACTION PROBLEMS; PROLOG (PROGRAMMING LANGUAGE); TIMING CIRCUITS; LOGIC PROGRAMMING;

CONSTRAINT LOGIC PROGRAMMING; DELAY CORRELATION; INTERVAL ARITHMETIC; TIMING CONSTRAINTS; TIMING DELAY; TIMING VERIFICATION; CONSTRAINT-SATISFACTION PROBLEMS; EARLY TYPES; LATE-TYPE; LINEAR TYPES; SIMPLE++;

LOGIC PROGRAMMING; CONSTRAINT PROGRAMMING;

EID: 85029657667     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/edtc.1997.582324     Document Type: Conference Paper

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