High-bandwidth address translation for multiple-issue processors

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 1996, Pages 158-167

  Austin, Todd M ^a   Sohi, Gurindar S ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; COMPUTER SIMULATION; COMPUTER SYSTEMS PROGRAMMING; MICROCOMPUTERS; MULTIPROCESSING SYSTEMS; PROGRAM TRANSLATORS; STORAGE ALLOCATION (COMPUTER); VIRTUAL STORAGE; MICROPROCESSOR CHIPS;

ADDRESS TRANSLATION; MULTIPLE ISSUE PROCESSORS; PIGGYBACK PORTS; TRANSLATION LOOKASIDE BUFFER;

COMPUTER ARCHITECTURE; MULTIPROCESSING SYSTEMS;

ADDRESS TRANSLATION; MULTIPLE ISSUE PROCESSORS; TRANSLATION LOOKASIDE BUFFER (TLB);

EID: 0029666635     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/232973.232990     Document Type: Conference Paper

References (0)