Carrier lifetime extraction in fully depleted dual-gate SOI devices

IEEE Electron Device Letters

Volumn 20, Issue 5, 1999, Pages 209-211

  Ernst, T ^a,b   Vandooren, A ^c   Cristoloveanu, S ^a   Colinge, J P ^c   Flandre, D ^d  

^a Grenoble INP Phelma   (France)

^b STMICROELECTRONICS   (France)

^c University of California Davis   (United States)

^d UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); HOT CARRIERS; LEAKAGE CURRENTS; SEMICONDUCTOR DIODES; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; THRESHOLD VOLTAGE;

CARRIER LIFETIME; CARRIER RECOMBINATION; DUAL GATE SILICON ON INSULATOR DEVICES; GATE ALL AROUND;

MOSFET DEVICES;

EID: 0032679920     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.761017     Document Type: Article

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