Design error diagnosis and correction in VLSI digital circuits

Midwest Symposium on Circuits and Systems

Volumn 2, Issue , 1997, Pages 1005-1008

  Veneris, Andreas G ^a   Hajj, Ibrahim N ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; ERROR CORRECTION; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; VECTORS;

DESIGN ERROR DIAGNOSIS AND CORRECTION (DEDC); TEST VECTOR SIMULATION;

VLSI CIRCUITS;

EID: 0031340853     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)