Compression/decompression DRAM for unified memory systems: A 16 Mb, 200 MHz, 90% to 50% graphics-bandwidth reduction prototype

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 342-343,-462

  Yabe, Y ^a   Aimoto, Y ^a   Motomura, M ^a   Takizawa, T ^a   Miyamoto, T ^a   Iwasaki, T ^a   Nakazawa, Y ^a   Fujii, T ^a   Hamada, M ^a   Nagai, N ^a   Yamashina, M ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; DATA COMPRESSION; IMAGE CODING; IMAGE COMPRESSION; INTERFACES (COMPUTER); STORAGE ALLOCATION (COMPUTER);

DYNAMIC RANDOM ACCESS MEMORY (DRAM); FRAME BUFFERS;

RANDOM ACCESS STORAGE;

EID: 0031700429     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)