Design optimization of vlsi array processor architecture for window image processing

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E82-A, Issue 8, 1999, Pages 1475-1483

  Dongju, L I ^a   Jiang, Li ^a   Kunieda, Hiroaki ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Array processor; Image processing; Systolic array; Window operation

Indexed keywords

ALGORITHMS; DATA STORAGE EQUIPMENT; IMAGE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; OPTIMIZATION; STANDARDS; SYSTOLIC ARRAYS;

MEMORY SHARING PROCESSOR ARRAYS (MSPA); MOTION PICTURE EXPERTS GROUP (MPEG) STANDARDS;

VLSI CIRCUITS;

EID: 0032596348     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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