Interface roughness effects in ultra-thin tunneling oxides

VLSI Design

Volumn 8, Issue 1-4, 1998, Pages 47-51

  Ting, D Z Y ^a,b   Daniel, Erik S ^b,c   McGill, T C ^b,d  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^c RICE UNIVERSITY   (United States)

^d California Institute of Technology   (United States)

Author keywords

Interface roughness; Oxide; Tunneling; Ultrathin

Indexed keywords

ELECTRON TUNNELING; INTERFACES (MATERIALS); SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SURFACE ROUGHNESS; ULSI CIRCUITS; ULTRATHIN FILMS;

PLANAR SUPERCELL STACK METHOD (PSSM); ULTRATHIN TUNNELING OXIDES;

MIS DEVICES;

EID: 0032315020     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/1998/23567     Document Type: Article

References (8)

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