Design for testability method using RTL partitioning

Proceedings of the Asian Test Symposium

Volumn , Issue , 1996, Pages 88-93

  Hosokawa, Toshinori ^a   Kawaguchi, Kenichi ^a   Ohta, Mitsuyasu ^a   Muraoka, Michiaki ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION (ATPG); REGISTER TRANSFER LEVEL (RTL) PARTITIONING;

COMPUTATIONAL COMPLEXITY; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL MODELS; SHIFT REGISTERS;

LSI CIRCUITS;

EID: 0030394017     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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