Phase/frequency detectors for high-speed PLL applications

Electronics Letters

Volumn 34, Issue 22, 1998, Pages 2120-2121

  Jeon, Sang O ^a   Cheung, Tae Sik ^a   Choi, Woo Young ^a  

^a Yonsei University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; FLIP FLOP CIRCUITS; LOGIC GATES; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

PHASE FREQUENCY DETECTORS; RESETTABLE RATIOED LATCHES;

DETECTOR CIRCUITS;

EID: 0032180298     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19981493     Document Type: Article

References (5)

1. BEST, RE..: 'Phase-locked loops: Theory, design and applications' (McGraw-Hill, New York, 1984), pp.93-171
2. MANEATIS, J.G.: 'Low-jitter process-independent DLL and PLL based on self-biased techniques', IEEE J. Solid-State Circuits, 1996, 31, (11), pp. 1723-1732
3. KIM, S.J., LEE, K.H., MOON, Y.S., JEONG, D.K., CHOI, Y.H., and LIM, H.K.: 'A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL', IEEE J. Solid-State Circuits, 1997, 32, (5), pp. 691-700
4. RAZAVI, B.: 'Monolithic phase-locked loops and clock recovery circuits - Theory and design' (IEEE Press, 1996), pp. 21-28
5. CHANG, B.S., PARK, J.B., and KIM, W.C.: 'A 1.2GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops', IEEE J. Solid-State Circuits, 1996, 31, (5), pp. 749-752