Simulation of SOI devices and circuits using BSIM3SOI

IEEE Electron Device Letters

Volumn 19, Issue 9, 1998, Pages 323-325

  Sinitsky, Dennis ^b   Tang, Stephen ^b   Jangity, Arun ^b   Assaderaghi, Fariborz ^a,c   Shahidi, Ghavam ^a,c   Hu, Chenming ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY;

BODY CURRENT MODELS;

MOSFET DEVICES;

EID: 0032162934     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.709628     Document Type: Article

References (7)

1. Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P. K. Ko, and C. Hu, "A physical and scaleable I-V model in BSIM3v3 for analog/digital circuit simulation," IEEE Trans. Electron Devices, vol. 44, pp. 277-287, Feb. 1997.
2. K. Hui, M. Chan, F. Assaderaghi, C. Hu, and P.-K. Ko, "Body self bias in fully depleted and nonfully depleted SOI devices," in Proc. IEEE SOI Conf., 1994, pp. 65-66.
3. C. Hu, VLSI Electronics: Microstructure Science. New York: Academic, 1989, vol. 18, ch. 3.
4. H. Wann, P. Ko, and C. Hu, "A channel field model of SOI MOSFET," in Proc. 1993 VLSI Symp. Technology, Systems, and Applications, pp. 133-137.
5. S. Parke, J. E. Moon, H. C. Wann, P. K. Ko, and C. Hu, "Design for suppression of gate-induced drain leakage in LDD MOSFET's using a quasitwo-dimensional analytical model," IEEE Trans. Electron Devices, vol. 39, July 1992.
6. F. Assaderaghi, G. Shahidi, L. Wagner, M. Hsieh, M. Pelella, S. Chu, R. Dennard, and B. Davari, "Accurate measurement of pass-transistor leakage current in SOI MOSFET's," in Proc. IEEE SOI Conf., 1996, pp. 66-67.
7. F. Assaderaghi, G. Shahidi, M. Hargrove, K. Hathorn, H. Hovel, S. Kulkarni, W. Rausch, D. Sadana, D. Schepis, R. Schulz, D. Yee, J. Sun, R. Dennard, and B. Davari, "History dependence of nonfully depleted (NFD) digital SOI circuits," in Symp. VLSI Tech. Dig., 1996, pp. 122-123.