메뉴 건너뛰기




Volumn 25, Issue 1, 1998, Pages 17-35

Theoretical properties of LFSRs for built-in self test

Author keywords

Built in self test; Hardware test pattern generator; Linear feedback shift register

Indexed keywords

ERROR CORRECTION; ERROR DETECTION; FEEDBACK; SHIFT REGISTERS;

EID: 0032155868     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(98)00005-4     Document Type: Article
Times cited : (5)

References (57)
  • 1
    • 0019899097 scopus 로고
    • Design for testability - A survey
    • T.W. Williams, K.P. Parker, Design for testability - a survey, IEEE Trans. Comput. C-31 (1) (1982) 2-15.
    • (1982) IEEE Trans. Comput. , vol.C-31 , Issue.1 , pp. 2-15
    • Williams, T.W.1    Parker, K.P.2
  • 2
    • 0028396582 scopus 로고
    • Built-in self test for digital integrated circuits
    • March-April
    • V.D. Agrawal et al., Built-in self test for digital integrated circuits, AT&T Tech. J. 73 (2) (March-April 1994).
    • (1994) AT&T Tech. J. , vol.73 , Issue.2
    • Agrawal, V.D.1
  • 5
    • 0040814369 scopus 로고    scopus 로고
    • Utilization of on-line (concurrent) checkers during built-in self test and vice-versa
    • Jan.
    • S.K. Gupta, D.K. Pradhan, Utilization of on-line (concurrent) checkers during built-in self test and vice-versa, IEEE Trans. Computers 45 (1) (Jan. 1996).
    • (1996) IEEE Trans. Computers , vol.45 , Issue.1
    • Gupta, S.K.1    Pradhan, D.K.2
  • 6
    • 0021444275 scopus 로고
    • Verification testing - A pseudoexhaustive test technique
    • June
    • E.J. McCluskey, Verification testing - a pseudoexhaustive test technique, IEEE Trans. Computers C-33 (6) (June 1984).
    • (1984) IEEE Trans. Computers , vol.C-33 , Issue.6
    • McCluskey, E.J.1
  • 7
    • 0024090224 scopus 로고
    • Circuits for pseudo-exhaustive test pattern generation
    • Oct.
    • L.T. Wang, E.J. McCluskey, Circuits for pseudo-exhaustive test pattern generation, IEEE Trans. Comput. Aided Des. 7 (10) (Oct. 1988).
    • (1988) IEEE Trans. Comput. Aided Des. , vol.7 , Issue.10
    • Wang, L.T.1    McCluskey, E.J.2
  • 8
    • 0016962513 scopus 로고
    • About random fault detection of combinational networks
    • June
    • R. David, G. Blanchet, About random fault detection of combinational networks, IEEE Trans. Comput. (June 1976) 650-664.
    • (1976) IEEE Trans. Comput. , pp. 650-664
    • David, R.1    Blanchet, G.2
  • 9
    • 0020752337 scopus 로고
    • Random Pattern coverage Enhancement and Diagnosis for LSSD Logic Self Test
    • May
    • E.B. Eichebelger, E. Lindbloom, Random Pattern coverage Enhancement and Diagnosis for LSSD Logic Self Test, IBM J. Res. Dev. 27 (May 1983) 265-272.
    • (1983) IBM J. Res. Dev. , vol.27 , pp. 265-272
    • Eichebelger, E.B.1    Lindbloom, E.2
  • 11
    • 0023211129 scopus 로고
    • On computing optimized input probabilities for random tests
    • H.J. Wunderlich, On computing optimized input probabilities for random tests, Proc. Des Automation Conf., 1987, pp. 392-398.
    • (1987) Proc. des Automation Conf. , pp. 392-398
    • Wunderlich, H.J.1
  • 14
    • 0002158127 scopus 로고
    • LFSR based deterministic and pseudo-random test pattern generator structures
    • C. Dufaza, G. Cambon, LFSR based deterministic and pseudo-random test pattern generator structures, Proc. European Test Conf., 1991, pp. 27-34.
    • (1991) Proc. European Test Conf. , pp. 27-34
    • Dufaza, C.1    Cambon, G.2
  • 16
    • 0024934580 scopus 로고
    • Test set embedding in a built-in self-test environment
    • S.B. Akers, W. Jansz, Test set embedding in a built-in self-test environment, Proc. Int. Test Conf., 1989, pp. 257-263.
    • (1989) Proc. Int. Test Conf. , pp. 257-263
    • Akers, S.B.1    Jansz, W.2
  • 18
  • 19
    • 20544448901 scopus 로고    scopus 로고
    • Scan-based BIST with complete fault coverage and low hardware overhead
    • June
    • H.J. Wunderlich, G. Kiefer, Scan-based BIST with complete fault coverage and low hardware overhead, IEEE European Test Workshop, June 1996.
    • (1996) IEEE European Test Workshop
    • Wunderlich, H.J.1    Kiefer, G.2
  • 20
    • 0023845826 scopus 로고
    • Probability models for pseudorandom test sequences
    • Jan.
    • E.J. Cluskey et al., Probability models for pseudorandom test sequences, IEEE Trans. Computer-Aided Design, Jan. 1988.
    • (1988) IEEE Trans. Computer-Aided Design
    • Cluskey, E.J.1
  • 21
    • 0002376728 scopus 로고
    • Fault simulation for structured VLSI
    • Dec.
    • J.A. Waicukauski et al., Fault simulation for structured VLSI, VLSI Systems Design, Dec. 1985.
    • (1985) VLSI Systems Design
    • Waicukauski, J.A.1
  • 22
    • 0020752337 scopus 로고
    • Random pattern coverage enhancement and diagnosis for LSSD logic self test
    • May
    • E.B. Eichebelger, E. Lindbloom, Random pattern coverage enhancement and diagnosis for LSSD logic self test, IBM J. Res. Dev. 27 (May 1983) 265-272.
    • (1983) IBM J. Res. Dev. , vol.27 , pp. 265-272
    • Eichebelger, E.B.1    Lindbloom, E.2
  • 24
    • 84961240995 scopus 로고
    • Generation of vectors patterns through reseeding of multiple polynomial linear feedback shift registers
    • S. Hellebrand, S. Tarnick, J. Rajski, Generation of vectors patterns through reseeding of multiple polynomial linear feedback shift registers, Proc. Int. Test Conf., 1992, pp. 120-129.
    • (1992) Proc. Int. Test Conf. , pp. 120-129
    • Hellebrand, S.1    Tarnick, S.2    Rajski, J.3
  • 27
    • 0029713988 scopus 로고    scopus 로고
    • Generating deterministic unordered test patterns with counters
    • May
    • D. Kagaris, S. Tragoudas, Generating deterministic unordered test patterns with counters, Proc. VLSI Test Symp., May 1996, pp. 374-379.
    • (1996) Proc. VLSI Test Symp. , pp. 374-379
    • Kagaris, D.1    Tragoudas, S.2
  • 29
    • 0019666474 scopus 로고
    • Hardware test pattern generation for built-in testing
    • W. Daehn, J. Mucha, Hardware test pattern generation for built-in testing, Proc. of Int. Test Conf., 1981, pp. 110-113.
    • (1981) Proc. of Int. Test Conf. , pp. 110-113
    • Daehn, W.1    Mucha, J.2
  • 30
    • 0020832564 scopus 로고
    • A class of test generators for built-in-testing
    • M.E. Aboulhamid, E. Cerny, A class of test generators for built-in-testing, IEEE Trans. Comput., 1983, pp. 957-959.
    • (1983) IEEE Trans. Comput. , pp. 957-959
    • Aboulhamid, M.E.1    Cerny, E.2
  • 32
    • 0021576191 scopus 로고
    • Built-in test for CMOS circuits
    • W. Starke, Built-in test for CMOS circuits, Proc. Int. Test Conf., 1984, pp. 309-314.
    • (1984) Proc. Int. Test Conf. , pp. 309-314
    • Starke, W.1
  • 34
    • 0346553580 scopus 로고
    • LFSROM an algorithm for automatic design synthesis of hardware test pattern generator
    • April
    • C. Dufaza, C. Chevalier, L.F.C. Lew Yan Voon, LFSROM an algorithm for automatic design synthesis of hardware test pattern generator, Proc. VLSI Test Symp., April 1993, pp. 208-214.
    • (1993) Proc. VLSI Test Symp. , pp. 208-214
    • Dufaza, C.1    Chevalier, C.2    Lew Yan Voon, L.F.C.3
  • 35
    • 84939371489 scopus 로고
    • On delay fault testing in logic circuits
    • Sept.
    • C.J. Lin, S.M. Reddy, On delay fault testing in logic circuits, IEEE Trans. Comput. Aided Design, 6 (5) (Sept. 1987) 694-703.
    • (1987) IEEE Trans. Comput. Aided Design , vol.6 , Issue.5 , pp. 694-703
    • Lin, C.J.1    Reddy, S.M.2
  • 37
    • 0022307908 scopus 로고
    • Model for delay faults based upon paths
    • Nov.
    • G.L. Smith, Model for delay faults based upon paths, Proc. Int. Test Conf., Nov. 1985, pp. 342-349.
    • (1985) Proc. Int. Test Conf. , pp. 342-349
    • Smith, G.L.1
  • 38
    • 0001892982 scopus 로고
    • Accumulator-based BIST approach for stuck-open and delay faults testing
    • I. Voyiatzis et al., Accumulator-based BIST approach for stuck-open and delay faults testing, Proc. European Des. Test Conf., 1995, pp. 431-435.
    • (1995) Proc. European Des. Test Conf. , pp. 431-435
    • Voyiatzis, I.1
  • 39
    • 0022306482 scopus 로고
    • Pseudo-exhaustive adjacency testing: A BIST approach for stuck-open faults
    • Oct.
    • G.L. Craig, C.R. Kime, Pseudo-exhaustive adjacency testing: a BIST approach for stuck-open faults, Proc. Int. Test Conf., Oct. 1985, pp. 126-137.
    • (1985) Proc. Int. Test Conf. , pp. 126-137
    • Craig, G.L.1    Kime, C.R.2
  • 41
    • 33845420031 scopus 로고
    • A BIST approach to delay fault testing with reduced test length
    • B. Wurth, K. Fuchs, A BIST approach to delay fault testing with reduced test length, Proc. European Des. Test Conf., 1995, pp. 418-483.
    • (1995) Proc. European Des. Test Conf. , pp. 418-483
    • Wurth, B.1    Fuchs, K.2
  • 42
    • 0026618765 scopus 로고
    • Two-pattern test capabilities of autonomous TPG Circuits
    • K. Furuya, E.J. McCluskey, Two-pattern test capabilities of autonomous TPG Circuits, Proc. Int. Test Conf., 1991, pp. 704-711.
    • (1991) Proc. Int. Test Conf. , pp. 704-711
    • Furuya, K.1    McCluskey, E.J.2
  • 43
    • 0028723078 scopus 로고
    • Evaluations of various TPG circuits for use in two-pattern testing
    • May
    • K. Furuya, S. Yamazaki, M. Sato, Evaluations of various TPG circuits for use in two-pattern testing, Proc. VLSI Test Symp., May 1994, 242-247.
    • (1994) Proc. VLSI Test Symp. , pp. 242-247
    • Furuya, K.1    Yamazaki, S.2    Sato, M.3
  • 44
    • 0028135829 scopus 로고
    • BIST test pattern generators for stuck-open and delay testing
    • C. Chen, S.K. Gupta, BIST test pattern generators for stuck-open and delay testing, Proc. European Des. Test Conf., 1994, pp. 289-296.
    • (1994) Proc. European Des. Test Conf. , pp. 289-296
    • Chen, C.1    Gupta, S.K.2
  • 45
    • 0004838718 scopus 로고
    • BIST generators for sequential faults
    • S. Zhang, R. Byrne, D.M. Miller, BIST generators for sequential faults, Proc. ICCD, 1992, pp. 260-263.
    • (1992) Proc. ICCD , pp. 260-263
    • Zhang, S.1    Byrne, R.2    Miller, D.M.3
  • 46
    • 0002987089 scopus 로고
    • GLFSR - A new test pattern generator for built-in self test
    • D.K. Pradhan, M. Chatterjee, GLFSR - a new test pattern generator for built-in self test, Proc. Int. Test Conf., 1994, pp. 481-490.
    • (1994) Proc. Int. Test Conf. , pp. 481-490
    • Pradhan, D.K.1    Chatterjee, M.2
  • 48
    • 0000197045 scopus 로고    scopus 로고
    • BIST test pattern generators for two-pattern testing - Theory and design algorithms
    • March
    • C. Chen, S.K. Gupta, BIST test pattern generators for two-pattern testing - theory and design algorithms, IEEE Trans. Comput. 45 (3) (March 1996) 257-269.
    • (1996) IEEE Trans. Comput. , vol.45 , Issue.3 , pp. 257-269
    • Chen, C.1    Gupta, S.K.2
  • 49
    • 0028734869 scopus 로고
    • Weighted random robust path delay testing of synthesized multilevel circuits
    • May
    • W. Wang, S.K. Gupta, Weighted random robust path delay testing of synthesized multilevel circuits, Proc. VLSI Test Symp., May 1994, pp. 291-297.
    • (1994) Proc. VLSI Test Symp. , pp. 291-297
    • Wang, W.1    Gupta, S.K.2
  • 51
    • 0011409771 scopus 로고
    • The theory of error correcting codes
    • North-Holland, Amsterdam
    • F.J. McWilliams, N.J.A. Sloane, The theory of error correcting codes, Mathematical Library, North-Holland, Amsterdam, 1977.
    • (1977) Mathematical Library
    • McWilliams, F.J.1    Sloane, N.J.A.2
  • 57
    • 0030646141 scopus 로고    scopus 로고
    • On the generation of pseudo-deterministic two-patterns test sequence with LFSRs
    • C. Dufaza, Y. Zorian, On the generation of pseudo-deterministic two-patterns test sequence with LFSRs, Proc. Eur. Design Test Conf., 1997, 69-76.
    • (1997) Proc. Eur. Design Test Conf. , pp. 69-76
    • Dufaza, C.1    Zorian, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.