Large chip vs. MCM for a high-performance system

IEEE Micro

Volumn 18, Issue 4, 1998, Pages 33-41

  Davidson, Evan E ^a,b,c,d  

^a IBM   (United States)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^c NEW YORK UNIVERSITY   (United States)

^d IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COSTS; ELECTRIC WIRING; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); LITHOGRAPHY; MICROPROCESSOR CHIPS; MULTICHIP MODULES; SUBSTRATES; THIN FILMS;

ELECTROSTATIC STATIC DISCHARGE; INTERCONNECTION DELAY; MOORE LAW; SEMICONDUCTOR INDUSTRY;

ELECTRONICS PACKAGING;

EID: 0032114860     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.710869     Document Type: Article

References (10)

1. H.P. Hofstee et al., "Designing for a Gigahertz," IEEE Micro, May-June 1998, pp. 66-74.
2. The National Technology Roadmap for Semiconductors, Semiconductor Industry Assn., San Jose, Calif., 1997.
3. M.T. Bohr, "Interconnect Scaling - The Real Limiter to High Performance ULSI," Proc. 1995 Int'l Electron Device Meeting, IEEE, Piscataway, N.J., pp. 241-242.
4. 3) and Their Impact Upon Large Chip Performance," IEEE Trans. Components, Packaging and Manufacturing Technology - Part B, Vol. 20, No. 4, IEEE, Nov. 1997, pp. 361-375.
5. G.A. Sai-Halasz, "Performance Trends in High-End Processors," Proc. IEEE, Vol. 83, No. 1, IEEE, Jan. 1995, pp. 20-36.
6. G. George et al., "Packaging Alternatives to Large Silicon Chips: Tiled Silicon on MCM and PWB Substrates," IEEE Trans. Components, Packaging and Manufacturing Technology - Part B, Vol. 19, No. 4, IEEE, Nov. 1996, pp. 699-708.
7. Q. Zhu et al., "Package Clock Distribution Design Optimization for High Speed and Low Power VLSls," IEEE Trans. Components, Packaging and Manufacturing Technology - Part B, Vol. 20, No. 1, IEEE, Feb. 1997, pp. 56-63.
8. D. Patterson et al., "A Case for Intelligent RAM," IEEE Micro, Mar./Apr. 1997, pp. 34-44.
9. E.E. Davidson et al., "Physical and Electrical Design Features of the IBM ES/9000 Circuit Module," IBM J. Research and Development, Vol. 36, No. 5, Sept. 1992, pp. 877-888.
10. Microelectronics Packaging Handbook, Part 1, 2nd ed., R.R. Tummala et al., eds., Chapman-Hall, New York, 1998, Chap. 3, pp. 252-256.