Design and analysis of a ±1V CMOS four-quadrant analogue multiplier

IEE Proceedings: Circuits, Devices and Systems

Volumn 145, Issue 3, 1998, Pages 148-154

  Seng, Y K ^a   Rofail, S S ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Analogue circuit design; Circuit fabrication; Frequency doubters; Simulation

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC DISTORTION; ELECTRIC LOSSES; ELECTRIC NETWORK ANALYSIS; ELECTRIC RESISTANCE; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; TRANSISTORS;

FOUR QUADRANT ANALOG MULTIPLIERS;

LINEAR INTEGRATED CIRCUITS;

EID: 0032097112     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19981823     Document Type: Article

References (14)

1. LIN, L.T., ROSKY, D., and TRUONG, H.D.: 'A 9100 gate ECL/TTL compatible BiCMOS gate array.' Proceedings of IEEE CICC, 1987, pp. 190-194
2. QIN, S.C., and GEIGER, R.L.: 'A ±5 V CMOS analog multiplier,' IEEEJ. Solid-State Circuits. 1987, 22, (6), pp. 1143-1146
3. KIM, Y.H., and PARK, S.B.: 'Four-quadrant CMOS analogue multiplier', Electron. Lett., 1992, 28, (7), pp. 649-650
4. WONG, S.L., KALYANASUNDARAM, N., and SALAMA, C.A.T.: 'Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages', IEEE J. SolidSlate Circuits, 1986, SC-21, (6), pp. 1120-1122
5. PENA-FINOL, J., and CONNELLY, J.A.: 'A MOS four-quadrant analog multiplier using the quarter-square technique', IEEE J. Solul-Stale Circuits, 1987, SC-22, (6), pp. 1064-1073
6. SOO, D.C., and MEYER, R.G.: 'A four-quadrant NMOS analog multiplier', IEEE J. Solid-State Circuits, 1982, SC-17, (6), pp. 1174-1178
7. BABABEZHAD, J.N., and TEMES, G.G.: 'A 20V four-quadrant CMOS analog multiplier', IEEEJ. Solid-Slate Circuits, 1985, SC20, (6), pp. 1158-1168
8. LIU, S., and HWANG, Y.S.: 'CMOS four-quadrant multiplier using bias offset crosscoupled pairs', Electron. Lett., 1993, 29, pp. 1737-1738
9. WANG, Z.H.: 'A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance', IEEEJ. Solid-State Circuits, 1991, 26, (9), pp. 1293-1301
10. MASSENGILL, L.W.: 'A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation', IEEE J. Solid-State Circuits, 1991, 26, (3), pp. 268-276
11. BULT, K., and WALLINGA, H.: 'A CMOS four-quadrant analog multiplier', IEEEJ. Solid-State Circuits, 1986, SC-21, (3), pp. 430-435
12. LEE, S.T., YEO, K.S., ROFAIL, S.S., and LAU, K.T.: 'A ±1V four-quadrant analog BiCMOS multiplier.' Proceedings of ICS1CT, Beijing, China, 1995, pp. 772-774
13. HSPICE user's manual and quick referene guide (Meta-Software Inc., Campbell, CA 95008, USA, 1993)
14. McCREARY, J.L., and GRAY, P.R.: 'All-MOS charge redistribution analog-to-digital conversion technique', IEEE J. SolidState Circuits, 1975, SC-10, pp. 371-379