A MOS Four-Quadrant Analog Multiplier Using the Quarter-Square Technique

IEEE Journal of Solid-State Circuits

Volumn 22, Issue 6, 1987, Pages 1064-1073

  Peña Finol, Jesüs S ^a   Connelly, J Alvin ^b  

^a INTERSIL CORPORATION   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 41549133866     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1987.1052856     Document Type: Article

References (14)

1. J. B. Kuo, B. B. Lusignan, and R. W. Dutton, “An audio signal processing multiplier,” in Proc. Int. Symp. Circuits and Syst., May 1983, pp. 1257–1260.
2. M. Yasumoto and T. Enomoto, “Integrated MOS four-quadrant analogue multiplier using switched capacitor techniques,” Electron. Lett., vol. 18, pp. 669–771, Sept. 1982.
3. D. C. Soo and R. G. Meyer, “A four-quadrant NMOS analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1174–1178, Dec. 1982.
4. J. N. Babanezhad and G. C. Temes, “A 20-V four-quadrant CMOS analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1158–1168, Dec. 1985.
5. K. Bult and H. Wallinga, “A CMOS four-quadrant analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-21, no. 3, pp. 430–435, June 1986.
6. B. S. Song, “CMOS RF circuits for data communication applications,” IEEE J. Solid-State Circuits, vol. SC-21, no. 2, pp. 310–317, Apr. 1986.
7. G. A. Korn and T. M. Korn, Electronic Analog and Hybrid Computers. New York: McGraw-Hill, 1964, pp. 281–289.
8. “Special survey: Packaged analog multipliers,” Eng. Electron. Equipment, vol. 16, pt. 2, pp. 80–94, Nov. 1968.
9. B. Gilbert, “A high-performance monolithic multiplier using active feedback,” IEEE J. Solid-State Circuits, vol. SC-9, no. 6, pp. 364–373, Dec. 1974.
10. B. Gilbert, “A precision four-quadrant multiplier with subnanosecond response,” IEEE J. Solid-State Circuits, vol. SC-3, no. 6, pp. 353–365, Dec. 1968.
11. J. S. Peña-Finol and J. A. Connelly, “Quarter-square analog four-quadrant multiplier using MOS integrated circuit technology,” U.S. Patent 4 546 275, Oct. 1985.
12. J. S. Pefia-Finol and J. A. Connelly, “A four quadrant MOS analog multiplier,” in ISSCC Dig. Tech. Papers, Feb. 1987, pp. 214-215.
13. R. S. Muller and T. I. Kamins, Deoice Electronics for Integrated Circuits. New York: Wiley, 1977, pp. 352-354.
14. Y. Tsividis, “Design considerations in single-channel MOS analog integrated circuits—A tutorial.” IEEE J. Solid-State Circuits, vol. SC-3, no. 3, pp. 383-391, June 1978.