A hybrid methodology for switching activities estimation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 4, 1998, Pages 357-366

  Cheng, David I ^a   Cheng, Kwang Ting ^b   Wang, Deborah C ^c   Marek Sadowska, Malgorzata ^c  

^a Ultima Interconnect Technology   (United States)

^b University of California   (United States)

^c AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CORRELATION METHODS; DECISION THEORY; MATHEMATICAL MODELS; PROBABILITY; SWITCHING THEORY;

BINARY DECISION DIAGRAMS (BDD);

LOGIC CIRCUITS;

EID: 0032044923     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.703825     Document Type: Article

References (16)

1. R. Burch, F. Najm, P. Yang, and T. Trick, "McPOWER: A Monte Carlo approach to power estimation," in IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1992, pp. 90-97.
2. "A Monte Carlo approach for power estimation," IEEE Trans. VLSI Syst., vol. 1, pp. 63-71, Mar. 1993.
3. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, pp. 473-84, Apr. 1992.
4. D. I. Cheng, M. Marek-Sadowska, and K. T. Cheng, "Speeding up power estimation by topological analysis," in Proc. IEEE Customed Integrated Circuit Conf., May 1995, pp. 623-626
5. A. Ghosh, S. Devadas, K. Keutzer, and J. White, "Estimation of average switching activity in combinational and sequential circuits," in Proc. ACM/IEEE Design Automation Conf.. June 1992, pp. 253-259.
6. P. E. Landman and J. M. Rabaey, "Black-box capacitance models for architectural power analysis," in Proc. Int. Workshop on Low Power Design, Apr. 1994, pp. 165-170.
7. R. Marculescu, D. Marculescu, and M. Pedram, "Switching activity analysis considering spatiotemporal correlations," in IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1994, pp. 294-299.
8. C. M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation," in IEEE European Solid State Circuits Conf., 1990, pp. 61-64.
9. J. Monteiro, S. Devadas, B. Lin, C. Tsui, and M. Pedram, "Exact and approximate methods of switching activity estimation in sequential logic circuits," in Proc. Int. Workshop Low Power Design, Apr. 1994, pp. 117-122.
10. F. N. Najm, "Transition density, a stochastic measure of activity in digital circuits," in Proc. ACM/IEEE Design Automation Conf., June 1991, pp. 644-649.
11. E. Sentovich et al., "SIS: A system for sequential circuit synthesis," Memo. UCB/ERL M92/41, Univ. California, Berkeley.
12. S. C. Seth, L. Pan, and V. D. Agrawal, "Predict: probabilistic estimation of digital circuit testability," in Proc. Fault-Tolerant Computing Symp., 1985, pp. 220-225.
13. S. C. Seth, B. B. Bhattacharya, and V. D. Agrawal, "An exact analysis for efficient computation of random pattern testability in combinational circuits," in Proc. Fault-Tolerant Computing Symp., 1986, pp. 318-323.
14. C. Y. Tsui, M. Pedram, and A. M. Despain, "Efficient estimation of dynamic power consumption under a real delay model," in IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1993, pp. 224-228.
15. C. Y. Tsui, J. Monteiro, M. Pedram, S. Devadas, A. Despain, and B. Lin, "Power estimation methods for sequential logic circuits," IEEE Trans. VLSI Syst., Sept. 1995, pp. 404-16.
16. M. Xakellis and F. Najm, "Statistical estimation of the switching activity in digital circuits," in Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 728-733.