Speeding up power estimation by topological analysis

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1995, Pages 623-626

  Cheng, David Ihsin ^a   Marek Sadowska, Malgorzata ^a   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK PARAMETERS; ELECTRIC NETWORK TOPOLOGY; LOGIC GATES; PARAMETER ESTIMATION;

POWER ESTIMATION; SUPERGATES CONCEPT; TOPOLOGICAL ANALYSIS;

COMBINATORIAL CIRCUITS;

EID: 0029216459     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)