Optimal usage of available wiring resources in diffractive–reflective optoelectronic multichip modules

Applied Optics

Volumn 37, Issue 2, 1998, Pages 233-253

  Cruz Rivera, José L ^a   Wills, D Scott ^b   Gaylord, Thomas K ^b   Glytsis, Elias N ^b  

^a UNIVERSITY OF PUERTO RICO   (Puerto Rico)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC WIRING; FIBER OPTIC NETWORKS; FLIP CHIP DEVICES; INTERCONNECTION NETWORKS; LENSES; MULTICHIP MODULES; NUMERICAL METHODS; OPTICAL LINKS; OPTOELECTRONIC DEVICES; PARALLEL PROCESSING SYSTEMS; SUBSTRATES; VLSI CIRCUITS;

OPTOELECTRONIC LINK DELAY; OPTOELECTRONIC MULTICHIP MODULE;

OPTICAL INTERCONNECTS;

EID: 0031677618     PISSN: 1559128X     EISSN: 21553165     Source Type: Journal    
DOI: 10.1364/AO.37.000233     Document Type: Article

References (36)

1. “National technology roadmap for semiconductors, ” Tech. Rep., Semiconductor Industry Association, San Jose, Calif. (1994).
2. R. R. Tummala, “Multichip packaging—a tutorial, ” Proc. IEEE 80, 1924-1941 (1992).
3. M. R. Feldman, S. C. Esener, C. C. Guest, and S. H. Lee, “Comparison between optical and electrical interconnects based on power and speed considerations, ” Appl. Opt. 27, 1742-1751 (1988).
4. M. R. Feldman and C. C. Guest, “Interconnect density capabilities of computer generated holograms for optical interconnections of VLSI circuits, ” Appl. Opt. 28, 3134-3137 (1989).
5. M. R. Feldman, C. C. Guest, T. J. Drabik, and S. C. Esener, “Comparison between electrical and free-space optical interconnections for fine-grain processor arrays based on interconnect density capabilities, ” Appl. Opt. 28, 3820-3829 (1989).
6. M. R. Feldman and C. C. Guest, “Holograms for optical interconnects for very large scale integrated circuits fabricated by electron-beam lithography, ” Opt. Eng. 28, 915-921 (1989).
7. K. H. Brenner and F. Sauer, “Diffractive-reflective optical interconnects, ” Appl. Opt. 27, 4251-4254 (1988).
8. S. K. Patra, J. Ma, V. H. Ozguz, and S. H. Lee, “Alignment issues in packaging for free-space optical interconnects, ” Opt. Eng. 33, 1561-1570 (1994).
9. J. Fan, B. Catanzaro, V. H. Ozguz, C. K. Cheng, and S. H. Lee, “Design considerations and algorithms for partitioning optoelectronic multichip modules, ” Appl. Opt. 34, 3116-3127 (1995).
10. J. Fan, B. Catanzaro, F. Kiamilev, S. C. Esener, and S. H. Lee, “Architecture of an integrated computer-aided design system for optoelectronics, ” Opt. Eng. 33, 1571-1580 (1994).
11. L. J. Camp, R. Sharma, and M. R. Feldman, “Guided-wave and free-space optical interconnects for parallel-processing systems: a comparison, ” Appl. Opt. 33, 6168-6180 (1994).
12. W. J. Dally, “Performance analysis of k-ary re-cube interconnection networks, ” IEEE Trans. Comput. 39, 775-785 (1990).
13. A. Agarwal, “Limits on interconnection network performance, ” IEEE Trans. Parallel Distribut. Syst. 2, 398-412 (1991).
14. S. Abraham and K. Padmanabhan, “Performance of multicomputer networks under pin-out constraints, ” J. Parallel Distribut. Comput. 12, 237-248 (1991).
15. S. L. Scott and J. R. Goodman, “The impact of pipelined channels on k-ary re-cube networks, ” IEEE Trans. Parallel Distribut. Syst. 5, 2-16 (1994).
16. D. Basak and D. K. Panda, “Designing clustered multiprocessor systems under packaging and technological advancements, ” IEEE Trans. Parallel Distribut. Syst. 7, 962-978 (1996).
17. M. Raksapatcharawong and T. M. Pinkston, “An optical interconnect model for k-ary re-cube wormhole networks, ” in Pro-ceediregs of the Tereth Ireterreatioreal Parallel Processireg Symposium (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 666-672.
18. J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, and E. N. Glytsis, “Architectural desin issues for optoelectronic k-ary re-cube interconnection networks, ” presented at the 1995 Optical Society of America Annual Meeting, Portland, Oregon, 10-15 September 1995.
19. J. L. Cruz-Rivera, W. S. Lacy, D. S. Wills, T. K. Gaylord, and E. N. Glytsis, “Performance modeling of optical interconnection technologies for massively parallel processing systems, ” in Proceediregs of the Third Ireterreatioreal Workshop ore Massively Parallel Processireg Usireg Optical Iretercorereectiores, A. Gottlieb, Y. Li, and E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif. 1996), pp. 264-275.
20. J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, and E. N. Glytsis, “Modeling the technology impact on the design of a two-level multicomputer interconnection network, ” in Proceediregs of the 1996 Ireterreatioreal Corefererece ore Computer Desigre (IEEE Computer Society, Los Alamitos, Calif. 1996), pp. 165-169.
21. K. H. Calhoun, C. B. Camperi-Ginestet, and N. M. Jokerst, “Vertical optical communication through stacked silicon wafers using hybrid monolithic thin film ingaasp emitters and detectors, ” IEEE Photon. Technol. Lett. 5, 254-257 (1993).
22. H. B. Bakoglu, Circuits, Iretercorereectiores, ared Packagireg for VLSI (Addison-Wesley, Reading, Mass., 1990).
23. J. W. Goodman, Iretroductiore to Fourier Optics (McGraw-Hill, San Francisco, 1968).
24. D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, and C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for multichip module interconnects, ” Appl. Opt. 33, 1444-1456 (1994).
25. D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. Lopez-Lagunas, and M. Hopper, “High throughput, low memory applications on the pica architecture, ” IEEE Trans. Parallel Distrib. Syst. 8, 1055-1067 (1997).
26. J. L. Cruz-Rivera, E. V. R. Di Bella, D. S. Wills, T. K. Gaylord, and E. N. Glytsis, “Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures, ” IEEE Trans. Med. Imag. 14, 758-762 (1995).
27. G. A. Sai-Halsz, “Performance trends in high-end processors, ” Proc. IEEE 83, 20-36 (1995).
28. V. J. Sferrino, “Multichip module study, ” Tech. Rep. TR9545 (MIT Lincoln Laboratory, Lexington, Mass. 1992).
29. K. Aoyama and A. A. Chien, “The cost of adaptivity and virtual lanes in a wormhole router, ” VLSI Design 2(4), 315-333 (1995).
30. D. C. Edelstein, G. A. Sai-Halsz, and Y.-J. Mii, “VLSI on-chip interconnection performance simulations and measurements, ” IBM J. Res. Develop. 39, 383-401 (1995).
31. W. J. Dally, “Express (c)ubes: improving the performance of k-ary re-cube interconnection networks, ” IEEE Trans. Comput. 40, 1016-1023 (1991).
32. R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, and T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms, ” J. Lightwave Technol. 10, 888-897 (1992).
33. 2-Si structure, ” in Microelectronic Interconnects and Packages: Optical and Electrical Technologies, G. Arjavalingam and J. Pazaris, eds., Proc. SPIE 1389, 408-421 (1990).
34. F. Sauer, “Fabrication of diffractive-reflective optical interconnects for infrared operation based on total internal reflection, ” Appl. Opt. 28, 386-388 (1989).
35. R. K. Kostuk, M. Kato, and Y.-T. Huang, “Polarization properties of substrate mode holographic interconnects, ” Appl. Opt. 29, 3848-3854 (1990).
36. W. S. Lacy, J. L. Cruz-Rivera, and D. S. Wills, “The offset cube: a three-dimensional multicomputer network topology using through-wafer optics, ” IEEE Trans. Parallel Distribut. Syst. (to be published).