MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 1, Issue , 1997, Pages 599-602

  Ooi, Yasushi ^a   Ohnishi, Osamu ^a   Yokoyama, Yutaka ^a   Katayama, Yoichi ^a   Mizuno, Masayuki ^a   Yamashina, Masakazu ^a   Takano, Hideto ^a   Hayashi, Naoya ^a   Tamitani, Ichiro ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BLOCK CODES; BUFFER STORAGE; IMAGE COMPRESSION; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); LSI CIRCUITS; MULTIPROCESSING SYSTEMS; RANDOM ACCESS STORAGE; SIGNAL TO NOISE RATIO;

MOTION PICTURE EXPERTS GROUP (MPEG) STANDARD; SINGLE MEMORY INTERFACES;

SIGNAL ENCODING;

EID: 0030696398     PISSN: 07367791     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)