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Volumn 39, Issue , 1996, Pages 354-355
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Dual floating point coprocessor with an FMAC architecture
a a |
Author keywords
[No Author keywords available]
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
COMPUTER HARDWARE;
ENCODING (SYMBOLS);
LOGIC DESIGN;
PIPELINE PROCESSING SYSTEMS;
SIGNAL ENCODING;
TIMING DEVICES;
CLOCK FREQUENCY;
FLOATING POINT UNIT;
INTEGER DATA FORMATS;
ROUTING CHANNELS;
MICROPROCESSOR CHIPS;
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EID: 0030086011
PISSN: 01936530
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (20)
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References (3)
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