RITUAL: A Performance-Driven Placement Algorithm

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 39, Issue 11, 1992, Pages 825-840

  Srinivasan, Arvind ^a   Chaudhary, Kamal ^a   Kuh, Ernest S ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; ELECTRIC WIRING; LSI CIRCUITS; MATHEMATICAL PROGRAMMING; SEQUENTIAL CIRCUITS;

CELL BASED ICS; CONSTRAINED PROGRAMMING; LAGRANGE RELAXATION; LSI DESIGN; PLACEMENT ALGORITHMS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0026944318     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.204130     Document Type: Article

References (44)

1. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison Wesley, 1990, ch. 9.
2. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison Wesley, 1990, ch. 5, pp. 202–211.
3. M. A. Breuer, “Min cut placement,” Design Automation and Fault-Tolerant Computing, 2, Oct. 1977.
4. J. R. Bunch and D. J. Rose, Eds., Sparse Matrix Computations. New York: Academic, 1976.
5. M. Burstein and M. N. Youssef, “Timing influenced layout design,” in IEEE Proc. 22nd Design Automation Conf., pp. 124–130, 1985.
6. C. K. Cheng and E. S. Kuh, “Module placement based on resistive network optimization,” IEEE Trans. Computer-Aided Design, vol. CAD-3, pp. 218–225, July 1984.
7. W. Donath and R. J. Norman et al., “Timing driven placement using complete path delays,” in IEEE Proc. 27th Design Automation Conf, 84–89, 1990.
8. A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. F. Juki, P. Kozak, and M. Wiesel, “Chip layout optimization using critical path weighting,” in IEEE Proc. 21st Design Automation Conf., pp. 133–136, 1984.
9. Y. A. El-Mansy and W. M. Siu, In Handbook of Semiconductor Technology and Computer Systems, Guy Rabbat, Ed. New York: Van Nostrand Reinhold, 1988.
10. M. L. Fisher, “Using duality to solve discrete optimization problems: Theory and computational experience,” Mathematical Programming Study, vol. 3, pp. 56–94, 1975.
11. M. L. Fisher, “An applications oriented guide to lagrangian relaxation,” INTERFACES, vol. 15, pp. 10–21, Mar.-Apr. 1985.
12. G. H. Golub and C. F. Van Loan, Matrix Computations. Balti-more, MD: Johns Hopkins University Press, 1989.
13. K. M. Hall, “An r-dimensional quadratic placement program,” Management Science, vol. 17, pp. 219–229, Nov. 1970.
14. P. S. Hauge, R. Nair, and E. J. Yoffa, “Circuit placement for predictable performance,” in Proc. IEEE Int. Conf. Computer-Aided Design, ICCAD-87, pp. 88–91, 1987.
15. M. Held and R. M. Karp, “The traveling-salesman problem and minimum spanning trees,” Operations Research, vol. 18, pp. 1138–1162, 1970.
16. M. Held, P. Wolfe, and H. P. Crowder, “Validation of subgradient optimization,” Mathematical Programming, vol. 6, pp. 62–88, 1974.
17. R. B. Hitchcock, G. L. Smith, and D. D. Cheng, “Timing analysis of computer hardware,” IBM J. Research and Development, vol. 26, pp. 100–105, 1983.
18. M. A. B. Jackson and E. S. Kuh, “Performance-driven placement of cell-based ICs,” in IEEE Proc. 26th Design Automation Conf, pp. 370–375, 1989.
19. J. M. Kleinhans, G. Sigl, and K. J. Antreich, “Gordian: VLSI placement by quadratic programming and slicing optimization,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 356–365, 1991.
20. E. L. Lawler, Combinatorial Optimization: Networks and Matroids. New York: Holt, Rinehart and Winston, 1976.
21. I. Lin and D. Du, “Performance driven constructive placement,” in IEEE Proc. 27th Design Automation Conf, pp. 103–105, 1990.
22. D. G. Luenberger, Linear and Nonlinear Programming. Reading, MA: Addison Wesley, 1984, 2nd edition, ch. 14.
23. M. Marek-Sadowska and S. P. Lin, “Timing-driven placement,” in Proc. IEEE Int. Conf. Computer-Aided Design ICCAD-89, pp. 94–97, 1989.
24. K. G. Murty, Linear Programming. New York: Wiley, 1983.
25. R. Nair, C. Leonard Berman, P. S. Hauge, and E. J. Yoffa, “Generation of performance constraints for layout,” in IEEE Trans. Computer-Aided Design, vol. 8, pp. 860–873, 1989.
26. Y. Ogawa et al, “Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSI's,” in IEEE Proc. 23rd Design Automation Conf, pp. 404–410, 1986.
27. M. Pedram, K. Chaudhary, and E. S. Kuh, “IO pad assignment based on circuit structure,” in Proc. Int. Conf. Computer Design, Oct. 1991.
28. S. Prasitjutrakul and W. J. Kubitz, “Path-delay constrained floor-planning: A mathematical programming approach for initial placement,” in IEEE Proc. 26th Design Automation Conf, pp. 364–369, 1989.
29. R. T. Rockafellar, Network Flows and Monotropic Optimization. New York: Wiley, 1984.
30. C. Sechen and K. W. Lee, “An improved simulated annealing algorithm for row-based placement,” in Proc. IEEE Int. Conf. Computer-Aided Design, pp. 478–481, Nov. 1988.
31. C. Sechen and A. Sangiovanni-Vincentelli, “The Timberwolf placement and routing package,” IEEE J. Solid-State Circuits, vol. 20, pp. 510–522, Apr. 1985.
32. E. M. Sentovich, “SIS: An interactive system for the synthesis of sequential logic circuits,” 1991, unpublished document.
33. J. F. Shapiro, Mathematical Programming: Structures and Algorithms. New York: Wiley, 1979.
34. R. Spickelmier, Ed., Oct Tools Distribution 2.1, Univ. California, Berkeley, Mar. 1988.
35. A. Srinivasan, “Performance optimization of large-scale integrated circuits,” Ph.D. dissertation, Univ. California, Berkeley, 1991.
36. S. Sutanthavibul and E. Shragowitz, “An adaptive timing driven layout for high speed VLSI,” in IEEE Proc. 27th Design Automation Conf, pp. 90–95, 1990.
37. S. Teig, R. L. Smith, and J. Seaton, “Timing-driven layout of cell-based IC's,” VLSI System's Design, pp. 63–73, May 1986.
38. R. S. Tsay, E. S. Kuh, and C. P. Hsu, “Proud: A sea-of-gates placement algorithm,” IEEE Design and Test of Computers, pp. 318–323, Dec. 1988.
39. M. Vecci and S. Kirkpatrick, “Global wiring by simulated annealing,” IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 215–222, Oct. 1983.
40. J. F. Wakerly, Digital Design: Principles and Practices. Englewood Cliffs, NJ: Prentice Hall, 1990.
41. P. K. Wolff, A. E. Ruehli, B. J. Agule, J. D. Lesser, and G. Goertzel, “Power/timing: Optimization and layout techniques for LSI chips,” J. Design Automation and Fault-Tolerant Computing, pp. 145–164, 1978.
42. H. Youssef, E. Shragowitz, and L. Bening, “Critical path issue in VLSI design,” in Proc. Int. Conf. Computer-Aided Design, pp. 520–523, 1989.
43. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. New York: Freeman.
44. J. B. Mazzola and A. W. Neebee, “Resource-constrained assignment scheduling,” Operations Research, vol. 34, pp. 560–572, July-Aug. 1986.