A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 11, 1997, Pages 1712-1718

  Shimomura, Ken'ichi ^a,b,d,e,f   Shimano, Hiroki ^b,d,g,h   Sakashita, Narumi ^b   Okuda, Fumihiro ^c   Oashi, Toshiyuki ^b   Yamaguchi, Yasuo ^b   Eimori, Takahisa ^b   Inuishi, Masahide ^b   Arimoto, Kazutami ^a,b   Maegawa, Shigeto ^b   Inoue, Yasuo ^b   Komori, Shinji ^a,b   Kyuma, Kazuo ^a,b  

^a IEEE   (Japan)

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

^c LTEC Corporation   (Japan)

^d Osaka University ^*

^e OSAKA UNIVERSITY   (Japan)

^f Advanced Technology R and D Center   (Japan)

^g KYOTO UNIVERSITY   (Japan)

^h Mitsubishi's Ctrl Res Laboratory   (Japan)

Author keywords

Circuit simulation; CMOS integrated circuits; DRAM chips; Integrated circuit design; Silicon on insulator technology

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; EQUALIZERS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC CIRCUITS; PULSE AMPLIFIERS; SILICON ON INSULATOR TECHNOLOGY;

BODY BIAS CONTROL; BODY CURRENT CLAMPER; BODY DRIVEN EQUALIZER; BODY PULSED SENSE AMPLIFIER; BODY PULSED TRANSISTOR LOGIC;

RANDOM ACCESS STORAGE;

EID: 0031270360     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641691     Document Type: Article

References (14)

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