SOI-DRAM circuit technologies for low power high speed multigiga scale memories

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 4, 1996, Pages 586-591

  Kuge, Shigehiro ^b,c   Morishita, Fukashi ^b,d   Tsuruda, Takahiro ^b,e,f   Tomishima, Shigeki ^b,g   Tsukude, Masaki ^b,h   Yamagata, Tadato ^a,b,f,g,i   Arimoto, Kazutami ^b,g,i  

^a IEEE

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

^c KYUSHU UNIVERSITY   (Japan)

^d KEIO UNIVERSITY   (Japan)

^e OKAYAMA UNIVERSITY   (Japan)

^f ULSI Laboratory

^g OSAKA UNIVERSITY   (Japan)

^h HIROSHIMA UNIVERSITY   (Japan)

ⁱ TOHOKU UNIVERSITY

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOSFET DEVICES; REDUNDANCY; SEMICONDUCTING SILICON; SEMICONDUCTOR STORAGE; SILICON ON INSULATOR TECHNOLOGY;

BODY BIAS CONTROLLING; HIGH SPEED CIRCUIT OPERATION; STANDBY CURRENT; SUPER BODY SYNCHRONOUS SENSING;

RANDOM ACCESS STORAGE;

EID: 0030122630     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.499736     Document Type: Article

References (12)

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3. M. Horiguchi et al., "An experimental 220 MHz 1 Gb DRAM," presented at ISSCC 95, session 14.5.
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