New write/erase operation technology for flash EEPROM cells to improve the read disturb characteristics

IEICE Transactions on Electronics

Volumn E80-C, Issue 10, 1997, Pages 1317-1323

  Endoh, Tetsuo ^a   Iizuka, Hirohisa ^b   Shirota, Riichirou ^a   Masuoka, Fujio ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

Flash memory; Read disturb characteristics; Stress leakage current; Write erase operation

Indexed keywords

ELECTRON TUNNELING; LEAKAGE CURRENTS; SEMICONDUCTOR STORAGE; SUBSTRATES;

FLASH MEMORY; WRITE/ERASE OPERATION METHODS;

PROM;

EID: 0031247617     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (14)

1. F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, and S. Tanaka, "A new flash EEPROM cell using triple polysilicon technology" IEEE Tech.Dig. of IEDM, pp. 464-467, 1984.
2. S. Tarn, S. Sachdev, M. Chi, G. Verma, J. Ziller, G. Tsau, S. Lai, and V. Dham, "A high density CMOS 1-T electrically erasable non-volatile (Flash) memory technology" 1988 Symposium on VLSI Technology, Technical papers, pp. 31-32.
3. T. Endoh, R. Shirota, S. Aritome, and F. Masuoka, "A study of high-performance NAND structured EEPROMs" IEICE Trans. Electron, vol. E75-C, pp. 1351-1357, 1992.
4. V. M. Bermudez, B. Euzent, N. Boruta, J. Lee, and C. Jenq, "Leakage current in thin oxide after stress" Pro. Int. Reliability Phys, Symp., pp. 11-16, 1981.
5. D. A. Baglee and M. C. Smayling, "The effects of write/ erase cycling on data Loss in EEPROMS" IEDM Tech. Dig., p. 624, 1985.
6. K. Naruke, S. Taguchi, and M. Wada, "Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness" IEDM Tech. Dig., pp. 424-427, 1988.
7. D. J. Dummin and R. Maddux, "Correlation of stressinduced leakage current in thin oxides with trap generation inside the oxides" IEEE Trans. Electron Devices, vol. ED-40, p.986, 1993.
8. P. Olivo, T. N. Nguyen, and B. Ricco, "High-field-induced degradation in ultra-thin SIO2 films" IEEE Trans. Electron Devices, vol. ED-38, p.527, 1991.
9. R. Mozzami and C. Hu, "Stress induced current in thin silicon dioxide films" IEDM Tech. Dig., p. 139, 1992.
10. M. Kimura and H. Koyama, "Stress-induced low-level leakage mechanism in ultrathin silicon dioxide films caused by neutral oxide trap generation" Proc. Int. Rel. Phys. Symp. (IRPS), p. 167, 1994.
11. T. Endoh, H. lizuka, S. Aritome, R. Shirota, and F. Masuoka, "New write/erase operation technology for flash EEPROM cells to improve the read disturb characteristics" IEDM Tech. Dig., pp. 603-606, 1992.
12. Q. D. M. Khosru, N. Yasuda, and K. Taniguchi, "Hole trapping and detrapping characteristics investigated by substrate hot-hole injection into oxide of metal-oxidesemiconductor structure" Jpn. J. Appl. Phys. vol. 33, p. 668, 1994.
13. R. Kirisawa, S. Aritome, R. Nakayama, T. Endoh, R. Shirota, and F. Masuoka, "A nand structured cell with a new programming technology for highly reliable 5V-only flash EEPROM" for VLSI Technology Dig. Tech. Papers, pp. 129-130, May 1990.
14. S. Aritome, R. Shirota, R. Kirisawa, T. Endoh, R. Nakayama, K. Sakui, and F. Masuoka, "A reliable bipolarity write/erase technology in flash EEPROMs" IEDM Tech. Dig., pp. 111-114, 1990.