Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 11, Issue 1, 1997, Pages 43-54

  Krstić, Angela ^a,b,c   Cheng, Kwang Ting ^a,c,d,e,f  

^a University of California   (United States)

^b UNIVERSITY OF BELGRADE   (Serbia)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f LUCENT TECHNOLOGIES   (United States)

Author keywords

Delay testing; Path delay faults; Resynthesis for testability; Timing defects; VLSI testing

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

PATH COUNT REDUCTION; PATH DELAY FAULT TESTABILITY;

COMBINATORIAL CIRCUITS;

EID: 0031206939     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008295716980     Document Type: Article

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