-
1
-
-
0030086602
-
"Multimedia complex on a chip,"
-
H. Sasaki, "Multimedia complex on a chip," IEEE ISSCC Dig. Tech. Pap., TA 1.1, pp. 16-19, Feb. 1996.
-
IEEE ISSCC Dig. Tech. Pap., TA 1.1, Pp. 16-19, Feb. 1996.
-
-
Sasaki, H.1
-
2
-
-
0003870436
-
"1-V microsystems - Scaling on schedule for personal communications,"
-
S. Malhi and P. Chatterjee, "1-V microsystems - Scaling on schedule for personal communications," IEEE Circuits and Devices, vol.10, no.2, pp.I3-17, March 1994.
-
IEEE Circuits and Devices, Vol.10, No.2, Pp.I3-17, March 1994.
-
-
Malhi, S.1
Chatterjee, P.2
-
3
-
-
0028447782
-
"MOSFET technology for low-voltage/low-power applications,"
-
D.P. Foty and E.J. Nowak, "MOSFET technology for low-voltage/low-power applications," IEEE Micro, vol.14, no.3, pp.68-76, June 1994.
-
IEEE Micro, Vol.14, No.3, Pp.68-76, June 1994.
-
-
Foty, D.P.1
Nowak, E.J.2
-
4
-
-
0027568889
-
"Prospects for multiple-valued integrated circuits,"
-
K.C. Smith and P.O. Gulak, "Prospects for multiple-valued integrated circuits," IEICE Trans. Electron., vol.E76-C, no.3, pp.372-382, March 1993.
-
IEICE Trans. Electron., Vol.E76-C, No.3, Pp.372-382, March 1993.
-
-
Smith, K.C.1
Gulak, P.O.2
-
6
-
-
0023997332
-
"A multiplier chip with multiple-valued bidirectional current-mode logic circuits,"
-
M. Kameyama, S. Kawahito, and T. Higuchi, "A multiplier chip with multiple-valued bidirectional current-mode logic circuits," IEEE Computer, 21, pp.43-56, April 1988.
-
IEEE Computer, 21, Pp.43-56, April 1988.
-
-
Kameyama, M.1
Kawahito, S.2
Higuchi, T.3
-
7
-
-
0027565403
-
"Prospects of multiple-valued VLSI processors,"
-
T. Hanyu, M. Kameyama, and T. Higuchi, "Prospects of multiple-valued VLSI processors," IEICE Trans. Electron., vol.E76-C, no.3, pp.383-392, March 1993.
-
IEICE Trans. Electron., Vol.E76-C, No.3, Pp.383-392, March 1993.
-
-
Hanyu, T.1
Kameyama, M.2
Higuchi, T.3
-
8
-
-
0029410535
-
"A 200 MHz pipelined multiplier using 1.5V-supply multiple-valued MOS currentmode circuits with dual-rail source-coupled logic,"
-
T. Hanyu and M. Kameyama, "A 200 MHz pipelined multiplier using 1.5V-supply multiple-valued MOS currentmode circuits with dual-rail source-coupled logic," IEEE J. Solid-State Circuits., vol.SC-30, no.ll, pp.1239-1245, Nov. 1995.
-
IEEE J. Solid-State Circuits., Vol.SC-30, No.ll, Pp.1239-1245, Nov. 1995.
-
-
Hanyu, T.1
Kameyama, M.2
-
9
-
-
0027866792
-
"An 8.8ns 54 x 54-bit multiplier using new redundant binary architecture,"
-
H. Makino, Y. Nakase, and H. Shinohara, "An 8.8ns 54 x 54-bit multiplier using new redundant binary architecture," IEEE Proc. Int. Conf. Computer Design, pp.202205, 1993.
-
IEEE Proc. Int. Conf. Computer Design, Pp.202205, 1993.
-
-
Makino, H.1
Nakase, Y.2
Shinohara, H.3
-
10
-
-
84937078021
-
"Signed-digit number representations for fast parallel arithmetic,"
-
A. Avizienis, "Signed-digit number representations for fast parallel arithmetic," IRE Trans. Elect. Comput., vol.EC10, no.3, pp.389-400, Sept. 1961.
-
IRE Trans. Elect. Comput., Vol.EC10, No.3, Pp.389-400, Sept. 1961.
-
-
Avizienis, A.1
|