Rectilinear Steiner trees with minimum Elmore delay

Proceedings - Design Automation Conference

Volumn , Issue , 1994, Pages 381-386

  Boese, Kenneth D ^a   Kahng, Andrew B ^a   McCoy, Bernard A ^a   Robins, Gabriel ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DELAY LINES; ELECTRIC WIRING; HEURISTIC METHODS; MINIMIZATION OF SWITCHING NETS; PERFORMANCE; TREES (MATHEMATICS); VLSI CIRCUITS;

ELMORE SINK DELAYS; RECTILINEAR STEINER TREES; STEINER OPTIMAL ROUTING TREE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0028552975     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/196244.196428     Document Type: Conference Paper

References (19)