Fast algorithm for performance-oriented Steiner routing

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1995, Pages 198-203

  Borah, Manjit ^a   Owens, Robert Michael ^a   Irwin, Mary Jane ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DATA STRUCTURES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS; MATHEMATICAL MODELS; MINIMIZATION OF SWITCHING NETS; TREES (MATHEMATICS);

CRITICAL SINKS; PERFORMANCE DRIVEN LAYOUT GENERATOR; PERFORMANCE-ORIENTED STEINER ROUTING;

DELAY CIRCUITS;

EID: 0029238204     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)