Design and low speed testing of a four-bit rsfq multiplier-accumulator

IEEE Transactions on Applied Superconductivity

Volumn 7, Issue 2 PART 3, 1997, Pages 3168-3171

  Herr, Quentin P ^a   Vukovic, Nada ^a   Mäncini, Cesar A ^a   Gaj, Kris ^a   Ke, Qing ^a   Adler, Victor ^a   Friedman, Eby G ^a   Krasniewski, Andrzej ^a   Bocko, Mark F ^a   Feldman, Marc J ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL FILTERS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; JOSEPHSON JUNCTION DEVICES; SYSTOLIC ARRAYS;

RAPID SINGLE FLUX QUANTUM (RSFQ) MULTIPLIER/ACCUMULATOR;

MULTIPLYING CIRCUITS;

EID: 0031164978     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.622003     Document Type: Article

References (20)

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