Interface circuits for chip-to-chip data transfer at ghz rates

IEEE Transactions on Applied Superconductivity

Volumn 7, Issue 2 PART 3, 1997, Pages 2657-2660

  Przybysz, John X ^a,b,c   Miller, Donald L ^a,b,c   Martinet, Stephen S ^a,b,c   Rang, Joonhee ^a,b,c   Hodge Worsham, A ^a,b,c   Farich, Michael L ^a,b,c  

^a NORTHROP GRUMMAN CORPORATION   (United States)

^b SCHLUMBERGER   (United States)

^c SolarLight Ltd   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CRITICAL CURRENT DENSITY (SUPERCONDUCTIVITY); DATA TRANSFER; DIGITAL INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; JOSEPHSON JUNCTION DEVICES; LOGIC GATES; QUANTUM ELECTRONICS; THRESHOLD LOGIC; TUNNEL DIODE AMPLIFIERS;

LATCHING AMPLIFIERS; SINGLE FLUX QUANTUM (SFQ) CIRCUITS;

LOGIC CIRCUITS;

EID: 0031163337     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.621785     Document Type: Article

References (7)

1. K.K. Ltkharev and V. K. Semenov RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems IEEE Transactions on Applied Superconductivity vol. 1 no. 1 pp. 3-28 March 1991.
2. NTT Electronics Technology Corp. Tokyo SELIC logic family model NLB6282.
3. H. Suzuki A. Inoue T. Imamura and S. Hasuo A Josephson driver to interface Josephson junctions to semiconductor transistors IEDM Tech. Dig. pp. 290-293 Dec. 1988.
4. John X. Przybysz Superconducting digital logic amplifier US Patent 4 859 879 August 22 1989.
5. Norio Fujimafci Seigo Kotani Takeshi Imamura and Shinya Hasuo Josephson Modified Variable Threshold Logic gates for use in ultra-high- | speed LSI IEEE Trans on Electron Devices vol. 36 no. 2 pp. 433-446 February 1989.
6. Daniel L. Meier John X. Przybysz and Joonhee Kang Fabrication of an '\ all-refractory circuit using lift-off with image-reversal photoresist IEEE Trans on Magnetics vol. 27 no. 2 pp. 3121-3124 March 1991.
7. J.X. Przybysz J. H. Kang D. L. Miller S. S. Martinet and A. H. Worsham Interface circuits for input and output of gigabit per second data Extended abstracts of 5th International Superconductive Electronics Conference pp. 304-306 Tokyo September 18-21 1995. j