Novel Octagonal Device Structure for Output Transistors in Deep-Submicron Low-Voltage CMOS Technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 889-892

  Ker, Ming Dou ^a   Wu, Tain Shun ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DEVICES; INTEGRATED CIRCUIT LAYOUT; BUFFER CIRCUITS; ELECTRIC CURRENTS; ELECTROSTATICS; RELIABILITY; TRANSISTORS;

'CURRENT; DEEP SUB-MICRON; DEEP SUBMICRONS; ESD ROBUSTNESS; LAYOUT AREA; LOW VOLTAGE CMOS TECHNOLOGY; NOVEL DEVICES; OUTPUT BUFFER; PER UNIT; TYPE DESIGNS;

GEOMETRY; SEMICONDUCTOR DEVICE STRUCTURES;

ELECTROSTATIC DISCHARGE; OUTPUT BUFFERS;

EID: 0030406633     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554122     Document Type: Conference Paper

References (3)

1. [l] S. Daniel and G. Krieger, “Process and design optimization for advanced CMOS I/O ESD protection devices,” 1990 EOSIESD SYWIP. P~oc.EOS-12, , pp. 206-213.
2. M.-D. Ker, T. 4. Wu, and K.-F. Wang, “N-sided polygonal cell layout for multiple cell transistor,” ROC Patent #076087.
3. M.-D. Ker, C.-Y. Wu, and H.-H. Chang, “ComplementaryLVTSCR ESD protection circuit for submicron CMOS VLSIAJLSI,” IEEE Trans. Electron Devices, vol. 43, no. 4, pp.588-598, 1996.