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Volumn , Issue , 1984, Pages 542-548
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SWITCH-LEVEL DELAY MODELS FOR DIGITAL MOS VLSI.
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NONE
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Author keywords
[No Author keywords available]
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Indexed keywords
CRITICAL PATHS;
CRYSTAL TIMING ANALYZERS;
DELAY ESTIMATES;
DELAY MODELING;
DIGITAL MOS VLSI;
SWITCH-LEVEL DELAY;
INTEGRATED CIRCUITS, VLSI;
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EID: 0021120602
PISSN: 01467123
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/dac.1984.1585850 Document Type: Conference Paper |
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Times cited : (59)
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References (0)
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