Modelling, analysis and synthesis of asynchronous control circuits using Petri nets

Integration, the VLSI Journal

Volumn 21, Issue 3, 1996, Pages 143-170

  Yakovlev, A V ^a   Koelmans, A M ^a   Semenov, A ^a   Kinniment, D J ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; PETRI NETS;

ASYNCHRONOUS CONTROL CIRCUITS; LOGIC SYNTHESIS; MICROPIPELINE; PETRI NET LEVEL DECOMPOSITION; SIGNAL TRANSITION GRAPH SPECIFICATIONS; SYNTAX DIRECTED TRANSLATION;

LOGIC CIRCUITS;

EID: 0030412962     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(96)00010-7     Document Type: Article

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