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Volumn , Issue , 1996, Pages 233-243

Control resynthesis for control-dominated asynchronous designs

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; DATA HANDLING; DIGITAL SIGNAL PROCESSING; HIGH LEVEL SYNTHESIS; PROGRAM TRANSLATORS; SYNTACTICS;

EID: 30244501684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1996.494454     Document Type: Conference Paper
Times cited : (22)

References (34)
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    • June
    • G. De Jong and B. Lin, A communicating Petri net model for the design of concurrent asynchronous modules. In ACM Design Automation Conference, June 1994.
    • (1994) ACM Design Automation Conference
    • De-Jong, G.1    Lin, B.2
  • 9
    • 0018005391 scopus 로고
    • Communicating sequential processes
    • C.A.R. Hoare. Communicating sequential processes. Communications of the ACM, 21:666-677,1978.
    • (1978) Communications of the ACM , vol.21 , pp. 666-677
    • Hoare, C.A.R.1
  • 12
    • 0029358772 scopus 로고
    • Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams
    • August
    • B. Lin and S. Devadas. Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. In IEEE Transactions on Computer-Aided Design, August 1995.
    • (1995) IEEE Transactions on Computer-Aided Design
    • Lin, B.1    Devadas, S.2
  • 13
    • 0028713073 scopus 로고
    • Synthesis of concurrent system interface modules with automatic protocol conversion generation
    • November
    • B. Lin and S. Vercauteren. Synthesis of concurrent system interface modules with automatic protocol conversion generation. In IEEE International Conference on Computer- Aided Design, November 1994.
    • (1994) IEEE International Conference on Computer- Aided Design
    • Lin, B.1    Vercauteren, S.2
  • 14
    • 0022879965 scopus 로고
    • Compiling communicating processes into delay-insensitive VLSI circuits
    • A. J. Martin. Compiling communicating processes into delay-insensitive VLSI circuits. Distributed Computing, 1:226-234,1986.
    • (1986) Distributed Computing , vol.1 , pp. 226-234
    • Martin, A.J.1
  • 15
    • 0003280654 scopus 로고
    • Synthesis of asynchronous VLSI circuits
    • North-Holland, ed. J. Straunstrup
    • A. J. Martin. Synthesis of asynchronous VLSI circuits. In Formal Methods for VLSI Design, North-Holland, ed. J. Straunstrup, 1990.
    • (1990) Formal Methods for VLSI Design
    • Martin, A.J.1
  • 27
    • 0002391456 scopus 로고
    • Delay insensitive codes-an overview
    • T. Verhoeff. Delay insensitive codes-an overview. Distributed Computing, 3:1-8,1988.
    • (1988) Distributed Computing , vol.3 , pp. 1-8
    • Verhoeff, T.1
  • 31
    • 0012022507 scopus 로고
    • Assassin: A synthesis system for asynchronous control circuits
    • IMEC, September. User and Tutorial manual
    • Ch. Ykman-Couvreur, B. Lin, and H. De Man. Assassin: A synthesis system for asynchronous control circuits. Technical report, IMEC, September 1994. User and Tutorial manual.
    • (1994) Technical Report
    • Ykman-Couvreur, C.1    Lin, B.2    De-Man, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.