Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits

Proceedings - 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1996

Volumn , Issue , 1996, Pages 222-232

  Pena M A ^a   Cortadella, J ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; ASYNCHRONOUS SEQUENTIAL LOGIC; LOGIC SYNTHESIS; PETRI NETS; TIMING CIRCUITS;

ASYNCHRONOUS CIRCUITS; AUTOMATIC SYNTHESIS; COMBINING PROCESS; DELAY MODELS; NEW APPROACHES; PROCESS ALGEBRAS; SIGNAL TRANSITION GRAPHS; SYNTHESIS METHOD;

DELAY CIRCUITS;

EID: 85043009264     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1996.494453     Document Type: Conference Paper

References (23)

1. V. Akella and G. Gopalakrishnan. SHILPA: A high-level synthesis system for self-timed circuits. In Proc. of the IEEE/ACM International Conference on Computer Aided Design, pages 587-591. IEEE Computer Society Press, November 1992.
2. E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In Proc. of the IEEE/ACM International Conference on Computer Aided Design, pages 262-265. IEEE Computer Society Press, November 1989.
3. T.-A. Chu. Synthesis of self-timed VLSI circuits from graph- theoretic specifications. In Proc. of the IEEE International Conference on Computer Design, pages 220-223. IEEE Computer Society Press, October 1987.
4. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Complete state encoding based on theory of regions. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, Aizu, Japan, March 1996.
5. J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Synthesizing Petri Nets from State-Based Models. In Proc. of the IEEE/ACM International Conference on Computer Aided Design, pages 164-171. IEEE Computer Society Press, November 1995.
6. G. de Jong and B. Lin. A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules. In Proc. ACM/IEEE Design Automation Conference, pages 4955, Jpne 1994.
7. J. C. Ebergen. Translating programs into delay-insensitive circuits, volume 56 of CWI Tract. Centre for Mathematics and Computer Science, 1989.
8. G. Gopalakrishnan, P. Kudva, E. Brunvand, and V. Akella. Peephole optimization of asynchronous macromodule networks. In Proc. of the IEEE International Conference on Computer Design, pages 442-446. IEEE Computer Society Press, October 1994.
9. C.A.R. Hoare. Communicating Sequential Processes. Prentice Hall International, 1989.
10. M. B. Josephs and J. T. Udding. An algebra for delay- insensitive circuits. In Robert P. Kurshan and Edmund M. Clarke, editors, Proc. International Workshop on Computer Aided Verification, volume 531 of Lecture Notes in Computer Science, pages 343-352. Springer-Verlag, 1990.
11. M. Kishinevsky, A. Kondratyev, A. Taubin, and V. Varshavsky. Concurrent Hardware. The Theory and Practice of Self-timed Design. Series in Parallel Computing. John Wiley & Sons, 1994.
12. A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed- independent circuits. In Proc. ACM/IEEE Design Automation Conference, pages 56-62, June 1994.
13. L. Lavagno and A. Sangiovanni-Vincentelli. Algorithms for Synthesis and Testing of Asynchronous Circuits. Kluwer Academic Publishers, 1993.
14. B. Lin, C. Ykman-Couvreur, and P. Vanbekbergen. A general state graph transformation framework for asynchronous synthesis. In Proc. European Design Automation Conference (EURO-DAC), pages 448-453. IEEE Computer Society Press, September 1994.
15. A. J. Martin. Compiling communicating processes into delay-insensitive VLSI circuits. Distributed Computing, l(4):226-234,1986.
16. M. A. Pena and J. Cortadella. Combining Process Algebras and Petri Nets for the Specification and Synthesis of Asynchronous Circuits. Technical Report RR-95/48, UPC/DAC, 1995.
17. I. Reicher and M. Yoeli. Net-based modeling of communicating parallel processes with applications to VLSI design. Technical Report 532, Technion-Israel Institute of Technology, December 1988.
18. L. Ya. Rosenblum and A. V. Yakovlev. Signal graphs: From self-timed to timed ones. In International Workshop on Tuned Petri Nets, pages 199-206, July 1985.
19. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. SIS: A system for sequential circuits synthesis. Technical Report M92/41, UCB/ERL, May 1992.
20. K. van Berkel. Handshake Circuits: an Asynchronous Architecture for VLSI Programming, volume 5 of International Series on Parallel Computation. Cambridge University Press, 1993.
21. K. van Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken, and F. Schalij. A fully-asynchronous low-power error corrector for the DCC player. IEEE Journal of Solid-State Circuits, 29(12):1429-1439, December 1994.
22. J. L. A. van de Snepscheut. Trace Theory and VLSI Design, volume 200 of Lecture Notes in Computer Science. Springer- Verlag, 1985.
23. G. Winskel. Petri Nets, Algebras, Morphisms, and Compositionality. Information and Computation, 7:197-238,1987.